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Home Teaching Courses WS 2003/2004 Seminar Technische Informatik

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Homepage zu dem Seminar für eingebettete Systeme im WS 03/04

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Termine

Vorbesprechung: 15.12.2003, 14:15, OH 16, E07

Durchführung: 10.-12.2.2004, jeweils 9:00-18:00

Vortragsreservierung: bei Frau Bauer, OH 16, E22, Tel. 6112

Themen

  1. Real-time Java I (Threads und Scheduling)
    Greg Bollella, Ben Brosgol, Peter Dibble, Steve Furr. James Gosling, David Hardin, Mark Turnbull, Rudy Belliardi: JSR-1: The Real-Time Specification for Java ¿, The Real-Time for Java Expert Group, http://www.rtj.org, Kap 1-4
  2. Real-time Java II (Speicherverwaltung und Synchronisation)
    a.o.a.O., Kap. 5, 6, 9, 10
  3. Real-time Java III (Zeitdienste)
    a.o.a.O., Kap. 7, 8, 11
  4. Message Sequence Charts I
    International Telecommunication Union (ITU): Formal description techniques (FDT) ¿ Message Sequence Chart, http://www.itu.int/ITU-T/studygroups/com10/languages/Z.120_1199.pdf
  5. Message Sequence Charts II
    a.o.a.O., Kap. 7-12
  6. Message Sequence Charts III
    a.o.a.O., Kap. 13-17
  7. Realzeit-UML I
    UML¿ Profile for Schedulability, Performance, and Time Specification http://www.omg.org/docs/ptc/02-03-02.pdf, Kap. 1-4
  8. Realzeit-UML II
    a.o.a.O., Kap. 5-7
  9. Realzeit-UML III
    a.o.a.O., Kap 8-10, Anhänge
  10. CAD-Unterstützung der Auswahl von A/D-Konvertern
    M. Vogels, G. Gielen: Architectural selection of A/D converters, Proceedings of the 40th conference on Design automation Conference (DAC), 2003, S. 974 ¿ 977;
    M. Vogels, G. Gielen: Figure of Merit based Selection of A/D converters, DATE, 2003, S. 1190-1191
  11. Global Asynchrone, Lokal Synchrone Prozessoren
    A. Iyer, D. Marculescu: Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors, http:// systems.cs.colorado.edu/ISCA2002/ FinalPapers/iyera_power_final.ps
  12. Diskrepanz zwischen Prozessor und Speichergeschwindigkeit
    P. Machanik: Approaches to addressing the memory wall. Technical Report, November 2002, Univ. Brisbane; http://www.itee.uq.edu.au/~philip/Publications/ Techreports/ 2002/Reports/memory-wall-survey.pdf
  13. Berechnung von worst case execution times (WCETs) I
    J. Blieberger, T. FAhringer, B. Scholz: Symbolic Cache Analysis for Real-Time Systems, http://citeseer.nj.nec.com/blieberger99symbolic.html, S. 1-21
  14. Berechnung von worst case execution times (WCETs) II
    a.o.a.O., S. 22-44