@inproceedings { DBLP:conf/date/RehmanSAKCH13,
  author = {Rehman, Semeen and Shafique, Muhammad and Aceituno, Pau Vilimelis and Kriebel, Florian and Chen, Jian-Jia and Henkel, J{\"o}rg},
  title = {Leveraging variable function resilience for selective software reliability on unreliable hardware},
  booktitle = {Design, Automation and Test in Europe, (DATE) 13, Grenoble, France, March 18-22, 2013},
  date-modified = {2015-08-27 13:34:22 +0000},
  year = {2013},
  keywords = {jj-old},
  confidential = {n},
}

@inproceedings { DBLP:conf/iccad/JahnPCH13,
  author = {Jahn, Janmartin and Pagani, Santiago and Chen, Jian-Jia and Henkel, J{\"o}rg},
  title = {MOMA: mapping of memory-intensive software-pipelined applications for systems with multiple memory controllers},
  booktitle = {The IEEE/ACM International Conference on Computer-Aided Design, (ICCAD), San Jose, CA, USA, November 18-21, 2013},
  date-modified = {2015-08-27 13:32:04 +0000},
  year = {2013},
  bdsk-url-1 = {http://dl.acm.org/citation.cfm?id=2561928},
  pages = {508-515},
  url = {http://dl.acm.org/citation.cfm?id=2561928},
  keywords = {jj-old},
  confidential = {n},
  abstract = {In many-core systems, the efficient deployment of computational and other resources is key in order to achieve a high throughput. Current state-of-the-art task mapping schemes balance the computational load among cores while avoiding congestions within the communication links. The problem is that a large number of cores running many memory-intensive tasks may congest memory controllers because their number and bandwidth is constrained. To avoid a high throughput degradation that could result from congested memory controllers, the mapping of tasks must be sensitized to the limited bandwidth of off-chip memory. Designing efficient and effective algorithms to optimize the throughput by jointly considering the load of memory controllers, computation, and communication is very challenging. In this paper, we address this problem by distributing cores among applications and then heuristically map tasks such that the load of the memory controllers is sufficiently balanced. Our heuristic also minimizes the effect of decreased throughput resulting from mapping communicating tasks to cores that belong to different controllers. Our experiments encourage us in that we can reduce the saturation of memory controllers and significantly increase the system throughput compared to employing several state-of-the-art task mapping schemes.},
}

@inproceedings { DBLP:conf/dac/JahnPKCH13,
  author = {Jahn, Janmartin and Pagani, Santiago and Kobbe, Sebastian and Chen, Jian-Jia and Henkel, J{\"o}rg},
  title = {Optimizations for configuring and mapping software pipelines in many core systems},
  booktitle = {The 50th Annual Design Automation Conference 2013, (DAC), Austin, TX, USA, May 29 - June 07, 2013},
  date-modified = {2015-08-27 13:32:07 +0000},
  year = {2013},
  bdsk-url-1 = {http://doi.acm.org/10.1145/2463209.2488894},
  pages = {130},
  url = {http://doi.acm.org/10.1145/2463209.2488894},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Efficiently utilizing the computational resources of many core systems is one of the most prominent challenges. The problem worsens when resource requirements vary unpredictably and applications may be started/stopped at any time. To address this challenge, we propose two schemes that calculate and adapt task mappings at runtime: a centralized, optimal mapping scheme and a distributed, hierarchical mapping scheme that trades optimality for a high degree of scalability. Experiments on Intel's 48-core Single-Chip Cloud Computer and in a many core simulator show that a significant improvement in system performance can be achieved over current state-of-the-art.},
}

@inproceedings { DBLP:conf/scopes/JahnKPCH13,
  author = {Jahn, Janmartin and Kobbe, Sebastian and Pagani, Santiago and Chen, Jian{-}Jia and Henkel, J{\"{o}}rg},
  title = {Runtime resource allocation for software pipelines},
  booktitle = {International Workshop on Software and Compilers for Embedded Systems, {M-SCOPES} '13, Sankt Goar, Germany, June 19-21, 2013},
  year = {2013},
  bdsk-url-1 = {http://doi.acm.org/10.1145/2463596.2486156},
  bdsk-url-2 = {http://dx.doi.org/10.1145/2463596.2486156},
  pages = {96--99},
  url = {http://doi.acm.org/10.1145/2463596.2486156},
  confidential = {n},
}

@inproceedings { DBLP:conf/sac/TomaC13,
  author = {Toma, Anas and Chen, Jian-Jia},
  title = {Computation offloading for real-time systems},
  booktitle = {Proceedings of the 28th Annual ACM Symposium on Applied Computing, SAC '13, Coimbra, Portugal, March 18-22, 2013},
  date-modified = {2015-08-27 13:31:50 +0000},
  year = {2013},
  bdsk-url-1 = {http://doi.acm.org/10.1145/2480362.2480670},
  pages = {1650-1651},
  url = {http://doi.acm.org/10.1145/2480362.2480670},
  keywords = {jj-old},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2013-toma-sac.pdf},
  confidential = {n},
  abstract = {Computation offloading has been adopted to improve the performance of embedded systems by offloading the computation of some tasks, especially computation-intensive tasks, to servers or clouds. This paper explores computation offloading for real-time embedded systems to decide which tasks should be offloaded to get the results in time. Such a problem is NP-complete even for frame-based real-time tasks with the same period and relative deadline. We develop a pseudo-polynomial-time algorithm for deriving feasible schedules, if they exist.},
}

@inproceedings { DBLP:conf/rtas/RehmanTKSCH13,
  author = {Rehman, Semeen and Toma, Anas and Kriebel, Florian and Shafique, Muhammad and Chen, Jian-Jia and Henkel, J{\"o}rg},
  title = {Reliable code generation and execution on unreliable hardware under joint functional and timing reliability considerations},
  booktitle = {19th IEEE Real-Time and Embedded Technology and Applications Symposium, (RTAS), Philadelphia, PA, USA, April 9-11, 2013},
  date-modified = {2015-08-27 13:32:35 +0000},
  year = {2013},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2013.6531099},
  pages = {273-282},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2013.6531099},
  keywords = {jj-old},
  confidential = {n},
  abstract = {To enable reliable embedded systems, it is imperative to leverage the compiler and system software for joint optimization of functional correctness, i.e., vulnerability indexes, and timing correctness, i.e., the deadline misses. This paper considers the optimization of the Reliability-Timing (RT) penalty, defined as a linear combination of the vulnerability indexes (reliability penalties) and the deadline misses. We propose a multi-layer approach to achieve reliable code generation and execution at compilation and system software layers for embedded systems. This is enabled by the concept of generating multiple versions, for given application functions, with diverse performance and reliability tradeoffs, by exploiting different reliability-guided compilation options. Based on the reliability and execution time profiling of these versions, our reliability-driven system software employs dynamic version selections to dynamically select a suitable version of a function according to the execution behavior of the previous functions. Specifically, our scheme builds a schedule table offline to optimize the RT penalty, and uses this table at run time to select suitable versions for the subsequent functions properly. A complex real-world application of ``secure video and audio processing'' composed of various functions is evaluated for reliable code generation and execution. The reliability analysis and evaluation is performed on a reliability-aware processor simulator.},
}

@inproceedings { DBLP:conf/aspdac/ChangCKF13,
  author = {Chang, Che-Wei and Chen, Jian-Jia and Kuo, Tei-Wei and Falk, Heiko},
  title = {Real-time partitioned scheduling on multi-core systems with local and global memories},
  booktitle = {18th Asia and South Pacific Design Automation Conference, (ASP-DAC) 2013, Yokohama, Japan, January 22-25, 2013},
  date-modified = {2015-08-27 13:32:28 +0000},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ASPDAC.2013.6509640},
  pages = {467-472},
  url = {http://dx.doi.org/10.1109/ASPDAC.2013.6509640},
  keywords = {jj-old},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2013-toma-estimedia.pdf},
  confidential = {n},
  abstract = {Real-time task scheduling becomes even more challenging with the emerging of island-based multi-core architecture, where the local memory module of an island offers shorter access time than the global memory module does. With such a popular architecture design in mind, this paper exploits real-time task scheduling over island-based homogeneous cores with local and global memory pools. Joint considerations of real-time scheduling and memory allocation are presented to efficiently use the computing and memory resources. A polynomial-time algorithm with an asymptotic 4-approximation bound is proposed to minimize the number of needed islands to successfully schedule tasks. To evaluate the performance of the proposed algorithm, 82 benchmarks from the MRTC, MediaBench, UTDSP, NetBench, and DSPstone benchmark suites were profiled by a worst-case-execution-time analyzer aiT and included in the experiments.},
}

@inproceedings { DBLP:conf/ecrts/TomaC13,
  author = {Toma, Anas and Chen, Jian-Jia},
  title = {Computation Offloading for Frame-Based Real-Time Tasks with Resource Reservation Servers},
  booktitle = {25th Euromicro Conference on Real-Time Systems, (ECRTS) 2013, Paris, France, July 9-12, 2013},
  date-modified = {2015-08-27 13:31:46 +0000},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ECRTS.2013.21},
  pages = {103-112},
  url = {http://dx.doi.org/10.1109/ECRTS.2013.21},
  keywords = {jj-old},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2013-toma-ecrts.pdf},
  confidential = {n},
  abstract = {Computation offloading concept has been recently adopted to improve the performance of embedded systems by moving some computation-intensive tasks (partially or wholly) to a powerful remote server. In this paper, we consider a computation offloading problem for frame-based real-time tasks, in which all the tasks have the same arrival time and the same relative deadline/period, by adopting the total bandwidth server (TBS) as resource reservations in the server side (remote execution unit). We prove that the problem is N P-complete and propose two algorithms in this paper. The first algorithm is a greedy algorithm with low complexity and provides a quick heuristic approach to decide which tasks to be offloaded and how the tasks are scheduled. The maximum finishing time of the solution derived from the greedy algorithm is at most twice of the finishing time (make span, maximal on the client and on the server) of any schedule. The second algorithm is a dynamic programming approach, which builds a three-dimensional table and requires pseudo-polynomial time complexity, to make an optimal decision for computation offloading. The algorithms are evaluated with a case study of a surveillance system and synthesized benchmarks.},
}

@inproceedings { DBLP:conf/estimedia/TomaC13,
  author = {Toma, Anas and Chen, Jian-Jia},
  title = {Server resource reservations for computation offloading in real-time embedded systems},
  booktitle = {The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), Montreal, QC, Canada, October 3-4, 2013},
  date-modified = {2015-08-27 13:32:40 +0000},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ESTIMedia.2013.6704500},
  pages = {31-39},
  url = {http://dx.doi.org/10.1109/ESTIMedia.2013.6704500},
  keywords = {jj-old},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2013-toma-estimedia.pdf},
  confidential = {n},
  abstract = {Mobile devices have become very popular nowadays. They are used nearly everywhere. They run complex applications where the multimedia data are heavily processed. For example, ubiquitous applications in smart phones and different surveillance tasks on mobile robots. However, most of these applications have real-time constraints, and the resources of the mobile devices are limited. So, it is challenging to finish such complex applications on these resource-constrained devices without violating the real-time constraints. One solution is to adopt the Computation Offloading concept by moving some computation-intensive tasks to a powerful server. In this paper, we use the total bandwidth server (TBS) as resource reservations in the server side, and propose two algorithms based on the computation offloading to decide which tasks to be offloaded and how they are scheduled, such that the utilization (i.e., bandwidth) required from the server is minimized. We consider frame-based real-time tasks, in which all the tasks have the same arrival time, relative deadline and period. The first algorithm is a greedy algorithm with low complexity based on a fast heuristic. The second one is a pseudo-polynomial-time algorithm based on dynamic programming. Finally, the algorithms are evaluated with a case study for surveillance system and synthesized benchmarks.},
}

@inproceedings { DBLP:conf/patmos/MunawarC13,
  author = {Munawar, Waqaas and Chen, Jian-Jia},
  title = {Peak power demand analysis and reduction by using battery buffers for monotonic controllers},
  booktitle = {23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Karlsruhe, Germany, September 9-11, 2013},
  date-modified = {2015-08-27 13:32:09 +0000},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.1109/PATMOS.2013.6662185},
  pages = {255-258},
  url = {http://dx.doi.org/10.1109/PATMOS.2013.6662185},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Demand of electricity varies on hourly basis whereas the production is quite inelastic. This results in fluctuating prices. Data centers and industrial consumers of electricity are penalized for the peak power demand of their loads. To shave the peak power demand, a battery buffer can be adopted. The battery is charged during low load and is discharged during peaks. One essential question is to analyze the reduction of the peak power demand by adopting battery buffers. The power loads are modeled in this paper by adopting the concept of arrival curves in Network Calculus. We analyze monotonic controllers, which have these two properties: (1) comparing one given trace of power loads and two initial battery statuses, if we start from higher battery status, the resulting battery status in the future will not become lower; (2) to increase the power demand at time slot t, the power loads released before t should be as close as possible to t. We present a simple and effective monotonic controller and also provide analyses for the peak power demand to the power grid. Our analysis mechanism can help determine the appropriate battery size for a given load arrival curve to reduce the peak.},
}

@inproceedings { DBLP:conf/rtcsa/PaganiC13,
  author = {Pagani, Santiago and Chen, Jian-Jia},
  title = {Energy efficiency analysis for the Single Frequency Approximation (SFA) scheme},
  booktitle = {IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, (RTCSA), Taipei, Taiwan, August 19-21, 2013},
  date-modified = {2015-08-27 13:31:53 +0000},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.1109/RTCSA.2013.6732206},
  pages = {82-91},
  note = {Best Paper Award},
  url = {http://dx.doi.org/10.1109/RTCSA.2013.6732206},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-efficient designs are important issues in computing systems. This paper studies the energy efficiency of a simple and linear-time strategy, called Single Frequency Approximation (SFA) scheme, for periodic real-time tasks on multi-core systems with a shared supply voltage in a voltage island. The strategy executes all the cores at a single frequency to just meet the timing constraints. SFA has been adopted in the literature after task partitioning, but the worst-case performance of SFA, in terms of energy consumption, is an open problem. We provide comprehensive analysis for SFA to derive the cycle utilization distribution for its worst-case behaviour for energy minimization. Our analysis shows that the energy consumption by using SFA for task execution is at most 1.53 (1.74, 2.10, 2.69, respectively), compared to the energy consumption of the optimal voltage/frequency scaling, when the dynamic power consumption is a cubic function of the frequency and the voltage island has up to 4 (8, 16, 32, respectively) cores. The analysis shows that SFA is indeed an effective scheme under practical settings, even though it is not optimal. Furthermore, since all the cores run at a single frequency and no frequency alignment for Dynamic Voltage and Frequency Scaling (DVFS) between cores is needed, any uni-core dynamic power management technique for reducing the energy consumption for idling can be easily incorporated individually on each core in the voltage island. This paper also provides the analysis of energy consumption for SFA, combined with the procrastination for Dynamic Power Management (DPM). Furthermore, we also extend our analysis for deriving the approximation factor of SFA for a multi-core system with multiple voltage islands.},
}

@inproceedings { DBLP:conf/rtss/PaganiC13,
  author = {Pagani, Santiago and Chen, Jian-Jia},
  title = {Energy Efficient Task Partitioning Based on the Single Frequency Approximation Scheme},
  booktitle = {IEEE 34th Real-Time Systems Symposium, (RTSS), Vancouver, BC, Canada, December 3-6, 2013},
  date-modified = {2015-08-27 13:32:00 +0000},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.1109/RTSS.2013.38},
  pages = {308-318},
  url = {http://dx.doi.org/10.1109/RTSS.2013.38},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-efficiency is a major concern in modern computing systems. For such systems, the presence of multiple voltage islands, where the voltage of each island can change independently and all cores in an island share the same supply voltage at any given time, is an expected compromise between global and per-core Dynamic Voltage and Frequency Scaling (DVFS). This paper focuses on energy minimization for a set of periodic tasks assigned on a voltage island. We present a simple and practical solution, that assigns the tasks onto cores in the island and then applies a DVFS schedule, particularly the Single Frequency Approximation (SFA) scheme. Furthermore, we provide thorough theoretical analysis of our solution, in terms of energy efficiency, against the optimal task partitioning and optimal DVFS schedule, especially for the state-of-the-art designs, that have a few number of cores per voltage island. The analysis shows that, our task partitioning scheme combined with SFA is a good and practical solution for energy efficiency. Particularly, when the number of cores in each voltage island is limited, the approximation factor is at most 2.01 (2.29, 2.55, 2.80, respectively) when the dynamic power consumption is a cubic function of the frequency and the islands have up to 4 (8, 16, 32, respectively) cores. Moreover, with non-negligible overhead for sleeping, further combination with any uni-core procrastination algorithm that consumes no more energy than keeping a core idle when it has no workload in its ready queue, increases the approximation factor by at most 1.},
}

@inproceedings { DBLP:conf/rtss/Chen13,
  author = {Chen, Jian-Jia},
  title = {Task Set Synthesis with Cost Minimization for Sporadic Real-Time Tasks},
  booktitle = {IEEE 34th Real-Time Systems Symposium, (RTSS), Vancouver, BC, Canada, December 3-6, 2013},
  date-modified = {2015-08-27 13:32:44 +0000},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.1109/RTSS.2013.42},
  pages = {350-359},
  url = {http://dx.doi.org/10.1109/RTSS.2013.42},
  keywords = {jj-old},
  confidential = {n},
  abstract = {By allowing users to specify multiple execution versions of a task with different amounts of worst-case execution time and costs, this paper explores how to minimize of the overall system cost under the timing constraints for sporadic real-time tasks. One specific application is to minimize the requirement scratchpad memory size (system cost) to meet the timing constraint, while the worst-case execution time of a task depends on its allocated scratchpad memory size. This paper shows that the problem is NP-hard for approximation, if speed augmentation is not allowed. The algorithms proposed in this paper are analyzed based on $(\alpha, \beta)$-approximation, in which a $\beta$ speed augmentation factor is allowed and the system cost is at most α times of the optimal solution. For tasks with constrained deadlines, an efficient ($1, 2/1-\eta$)-approximation algorithm based on dynamic programming is proposed for deadline-monotonic (DM) scheduling, where$ 0 < \eta < 1$ is a user-defined parameter for the rounding precision in dynamic programming. This is further extended to a ($1, 1.6322/1-\eta $)-approximation algorithm for earliest-deadline-first (EDF) scheduling. A polynomialtime ($1 + \epsilon, 1 + \eta$)-approximation scheme is also developed for EDF scheduling by considering $0 < \epsilon, 0 < \eta < 1$ when the ratio of the maximum relative deadline to the minimum relative deadline of tasks is a constant. This paper is concluded by considering the dual problem to maximize of the system profit by selecting execution versions with different amounts of worst-case execution time.},
}

@inproceedings { DBLP:conf/sies/FreierC13,
  author = {Freier, Matthias and Chen, Jian-Jia},
  title = {Prioritization for real-time embedded systems on dual-core platforms by exploiting the typical- and worst-case execution times},
  booktitle = {8th IEEE International Symposium on Industrial Embedded Systems, SIES 2013, Porto, Portugal, June 19-21, 2013},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.1109/SIES.2013.6601467},
  pages = {21-29},
  url = {http://dx.doi.org/10.1109/SIES.2013.6601467},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Adopting multicore platforms for real-time systems has recently been an active topic for both academia and industry. For hard real-time systems, the static worst-case execution time (WCET) analysis is usually needed for analyzing the schedulability. However, as the execution of a job depends on its input data, its internal state, and the architectural state, the worst-case execution time may be much larger than the typical execution time. Even though the jobs have unpredictable execution behavior, the practice now is to consider the feasibility and schedulability of the system based on their worst-case execution times. Therefore, the utilization of the system may be very low in most cases. This paper exploits a new scheme by adopting one core for executing tasks under their typical execution behavior, while the gap of the execution time between the typical case and the worst case is served on the other core. The objective is to use only one core most of time, whereas the second core is activated when it is necessary. We analyze the ineffectiveness when adopting the end-to-end deadline approaches in distributed systems for our studied problem. We show the connection of this problem to the well-known two-stage flowshop scheduling problem when considering frame-based real-time tasks, in which all the tasks have the same relative deadline and period. For general cases, in which tasks have different relative deadlines or periods, we provide a prioritization heuristic algorithm and its schedulability analysis. We also evaluate our algorithms to show the effectiveness.},
}

@inproceedings { DBLP:conf/smartgreens/WangMLC13,
  author = {Wang, Shengquan and Munawar, Waqaas and Liu, Xue and Chen, Jian-Jia},
  title = {Power-saving Design in Server Farms for Multi-tier Applications under Response Time Constraint},
  booktitle = {SMARTGREENS 2013 - Proceedings of the 2nd International Conference on Smart Grids and Green IT Systems, Aachen, Germany, 9-10 May, 2013},
  date-modified = {2015-08-27 13:32:13 +0000},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.5220/0004357201370148},
  pages = {137-148},
  url = {http://dx.doi.org/10.5220/0004357201370148},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Server farms suffer from an increasing power consumption nowadays. Power saving has become a prominent design issue in server farms. This paper presents a power-saving design in server farms under the constraint of the response time. In particular, we target on multi-tier applications, which are very typical on the web in modern days. We propose an efficient power-saving design strategy, called PowerTier. This strategy exploits two major techniques by using Dynamic Power management (DPM) to activate/deactivate servers and using Dynamic Voltage Scaling (DVS) to adjust the processor speed for each activated server. In addition, PowerTier considers two different application models: the open-queueing model and the closed-queueing model for session-less and session-based web applications respectively. With PowerTier, we are able to choose the number of activated servers at each tier and the processor speed for each server to minimize the overall power consumption in server farms while meeting a given mean response time guarantee for multi-tier applications. Our comprehensive simulation confirms the effectiveness and efficiency of PowerTier.},
}

@inproceedings { DBLP:conf/emsoft/ChangCMKF12,
  author = {Chang, Che-Wei and Chen, Jian-Jia and Munawar, Waqaas and Kuo, Tei-Wei and Falk, Heiko},
  title = {Partitioned scheduling for real-time tasks on multiprocessor embedded systems with programmable shared srams},
  booktitle = {Proceedings of the 12th International Conference on Embedded Software, EMSOFT 2012, part of the Eighth Embedded Systems Week, ESWeek 2012, Tampere, Finland, October 7-12, 2012},
  date-modified = {2015-08-27 13:31:31 +0000},
  year = {2012},
  bdsk-url-1 = {http://doi.acm.org/10.1145/2380356.2380384},
  pages = {153-162},
  url = {http://doi.acm.org/10.1145/2380356.2380384},
  keywords = {jj-old},
  confidential = {n},
  abstract = {This work is motivated by the advance of multiprocessor system architecture, in which the allocation of tasks over heterogeneous memory modules has a significant impact on the task execution. By considering two different types of memory modules with different access latencies, this paper explores joint considerations of memory allocation and real-time task scheduling to minimize the maximum utilization of processors of the system. For implicit-deadline sporadic tasks, a two-phase algorithm is developed, where the first phase determines memory allocation to derive a lower bound of the maximum utilization, and the second phase adopts worst-fit partitioning to assign tasks. It is shown that the proposed algorithm leads to a tight ($2-\frac{2}{M+1}$)-approximation bound where M is the number of processors. The proposed algorithm is then evaluated with 82 realistic benchmarks from MRTC, MediaBench, UTDSP, NetBench and DSPstone, and extensive simulations are further conducted to analyze the proposed algorithm.},
}

@inproceedings { DBLP:conf/ecrts/ChenC12,
  author = {Chen, Jian-Jia and Chakraborty, Samarjit},
  title = {Partitioned Packing and Scheduling for Sporadic Real-Time Tasks in Identical Multiprocessor Systems},
  booktitle = {24th Euromicro Conference on Real-Time Systems, ECRTS 2012, Pisa, Italy, July 11-13, 2012},
  date-modified = {2015-08-27 13:31:25 +0000},
  year = {2012},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/ECRTS.2012.43},
  pages = {24-33},
  url = {http://doi.ieeecomputersociety.org/10.1109/ECRTS.2012.43},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Multiprocessor platforms have been widely adopted to accommodate the increasing computation requirement of modern applications. Partitioned scheduling (or packing) has been widely exploited by partitioning real-time tasks onto processors to meet the timing constraints, which has been shown to be NP-complete in the strong sense. This paper studies the approximation of partitioned scheduling by exploiting resource augmentation with (1) speeding up or (2) allocating more processors. When adopting speeding up to meet timing constraints, we provide a polynomial-time approximation scheme (PTAS) to derive near-optimal solutions only with the assumption that the ratio of the maximum relative deadline to the minimum relative deadline is a constant. The previously known PTAS for this problem imposes additional restrictions on the periods and the execution times of tasks. By removing these additional constraints, our scheme can be adopted for wider task sets. When considering the resource augmentation by allocating more processors, we show that there does not exist any asymptotic polynomial-time approximation scheme (APTAS) unless P=NP.},
}

@inproceedings { DBLP:conf/rtas/WangMLCL12,
  author = {Wang, Shengquan and Munawar, Waqaas and Liu, Jun and Chen, Jian-Jia and Liu, Xue},
  title = {Power-Saving Design for Server Farms with Response Time Percentile Guarantees},
  booktitle = {2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, Beijing, China, April 16-19, 2012},
  date-modified = {2015-08-27 13:31:38 +0000},
  year = {2012},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2012.35},
  pages = {273-284},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2012.35},
  keywords = {jj-old},
  confidential = {n},
  abstract = {The expense of power cost in server farms has driven the recent power-aware development in both industry and academia. At the same time, a Service Level Agreement (SLA) of service performance between a customer and a service provider is demanded to meet the customer satisfaction. This paper investigates the queueing-theoretical power-saving design strategy for server farms under a given SLA, which in particular is measured in a certain level percentile of the job response time. We consider server farms with servers that are equipped with the capabilities of Dynamic Voltage Scaling (DVFS) and Dynamic Power Management (DPM). We adopt an M/G/1/PS server model, where the job service time distribution is assumed heavy-tailed, as discovered and validated by previous research. We propose a design strategy called Power Tail to minimize the power consumption under the given SLA. Our data confirms that the proposed Power Tail strategy indeed provides statistical guarantee in comparison with existing dynamic DVFS approaches and significantly outperforms the intuitive load-balancing strategy.},
}

@inproceedings { DBLP:conf/isaac/KaoCRW12,
  author = {Kao, Mong-Jen and Chen, Jian-Jia and Rutter, Ignaz and Wagner, Dorothea},
  title = {Competitive Design and Analysis for Machine-Minimizing Job Scheduling Problem},
  booktitle = {Algorithms and Computation - 23rd International Symposium, ISAAC 2012, Taipei, Taiwan, December 19-21, 2012. Proceedings},
  date-modified = {2015-08-27 13:31:18 +0000},
  year = {2012},
  bdsk-url-1 = {http://dx.doi.org/10.1007/978-3-642-35261-4_11},
  pages = {75-84},
  url = {http://dx.doi.org/10.1007/978-3-642-35261-4_11},
  keywords = {jj-old},
  confidential = {n},
  abstract = {We explore the machine-minimizing job scheduling problem, which has a rich history in the line of research, under an online setting. We consider systems with arbitrary job arrival times, arbitrary job deadlines, and unit job execution time. For this problem, we present a lower bound 2.09 on the competitive factor of any online algorithms, followed by designing a 5.2-competitive online algorithm. We would also like to point out a false claim made in an existing paper of Shi and Ye regarding a further restricted case of the considered problem. To the best of our knowledge, what we present is the first concrete result concerning online machine-minimizing job scheduling with arbitrary job arrival times and deadlines.},
}

@inproceedings { DBLP:conf/marc/JahnKPCH12,
  author = {Jahn, Janmartin and Kobbe, Sebastian and Pagani, Santiago and Chen, Jian-Jia and Henkel, J{\"o}rg},
  title = {Work in Progress: Malleable Software Pipelines for Efficient Many-core System Utilization},
  booktitle = {6th Many-core Applications Research Community (MARC) Symposium. Proceedings of the 6th MARC Symposium, 19-20 July 2012, Toulouse, France},
  date-modified = {2015-08-27 13:31:41 +0000},
  year = {2012},
  bdsk-url-1 = {http://hal.archives-ouvertes.fr/hal-00719027},
  pages = {30-33},
  url = {http://hal.archives-ouvertes.fr/hal-00719027},
  keywords = {jj-old},
  confidential = {n},
  abstract = {This paper details our current research project on the efficient utilization of many-core systems by utilizing applications based on a novel kind of software pipelines. These pipelines form malleable applications that can change their degree of parallelism at runtime. This allows not only for a well-balanced load, but also for an efficient distribution of the cores to the individual, competing applications to maximize the overall system performance. We are convinced that malleable software pipelines will significantly outperform existing mapping and scheduling solutions.},
}

@inproceedings { DBLP:conf/date/MasrurGCCAB12,
  author = {Masrur, Alejandro and Goswami, Dip and Chakraborty, Samarjit and Chen, Jian-Jia and Annaswamy, Anuradha and Banerjee, Ansuman},
  title = {Timing analysis of cyber-physical applications for hybrid communication protocols},
  booktitle = {2012 Design, Automation {\\&} Test in Europe Conference {\\&} Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012},
  date-modified = {2015-08-27 13:31:34 +0000},
  year = {2012},
  bdsk-url-1 = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6176681},
  pages = {1233-1238},
  url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6176681},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Many cyber-physical systems consist of a collection of control loops implemented on multiple electronic control units (ECUs) communicating via buses such as FlexRay. Such buses support hybrid communication protocols consisting of a mix of time- and event-triggered slots. The time-triggered slots may be perfectly synchronized to the ECUs and hence result in zero communication delay, while the event-triggered slots are arbitrated using a priority-based policy and hence messages mapped onto them can suffer non-negligible delays. In this paper, we study a switching scheme where control messages are dynamically scheduled between the time-triggered and the event-triggered slots. This allows more efficient use of time-triggered slots which are often scarce and therefore should be used sparingly. Our focus is to perform a schedulability analysis for this setup, i.e., in the event of an external disturbance, can a message be switched from an event-triggered to a time-triggered slot within a specified deadline? We show that this analysis can check whether desired control performance objectives may be satisfied, with a limited number of time-triggered slots being used.},
}

@inproceedings { DBLP:conf/iccad/ChenYC12,
  author = {Chen, Yi-Jung and Yang, Chia-Lin and Chen, Jian-Jia},
  title = {Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs},
  booktitle = {2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012},
  date-modified = {2015-08-27 13:31:21 +0000},
  year = {2012},
  bdsk-url-1 = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6386707},
  pages = {458-465},
  url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=6386707},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Stacking DRAMs on processing cores by Through-Silicon Vias (TSVs) provides abundant bandwidth and enables a distributed memory interface design. To achieve the best balance in performance and cost in an application-specific system, the distributed memory interface should be tailored for the target applications. In this paper, we propose the first distributed memory interface synthesis framework for application-specific Network-on-Chips (NoCs) with 3D-stacked DRAMs. To maximize the performance of a selected hardware configuration, the proposed framework co-synthesizes the hardware configuration of the distributed memory interface, and the software configuration, e.g. task mapping and data assignment. Since TSVs have adverse impact on chip costs and yields, the goal of the framework is minimizing the number of TSVs provided that the user-defined performance constraint is met.},
}

@inproceedings { DBLP:conf/marc/MunawarJACH11,
  author = {Munawar, Waqaas and Jahn, Janmartin and Aleinikov, Artiom and Chen, Jian-Jia and Henkel, J{\"o}rg},
  title = {An Empirical Feedback Provider for Multi Core Schedulers},
  booktitle = {3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, Ettlingen, Germany, July 5-6, 2011},
  date-modified = {2015-08-27 13:30:31 +0000},
  year = {2011},
  bdsk-url-1 = {http://digbib.ubka.uni-karlsruhe.de/volltexte/1000023937},
  pages = {69-70},
  url = {http://digbib.ubka.uni-karlsruhe.de/volltexte/1000023937},
  keywords = {jj-old},
  confidential = {n},
  abstract = {This manuscript includes recent scientific work regarding the Intel Single Chip Cloud computer and describes approaches for novel approaches for programming and run-time organization.},
}

@inproceedings { DBLP:conf/sac/ChenHT11,
  author = {Chen, Jian-Jia and Huang, Kai and Thiele, Lothar},
  title = {Power management schemes for heterogeneous clusters under quality of service requirements},
  booktitle = {Proceedings of the 2011 ACM Symposium on Applied Computing (SAC), TaiChung, Taiwan, March 21 - 24, 2011},
  date-modified = {2015-08-27 13:30:48 +0000},
  year = {2011},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1982185.1982304},
  pages = {546-553},
  url = {http://doi.acm.org/10.1145/1982185.1982304},
  keywords = {jj-old},
  confidential = {n},
  abstract = {For modern computer systems, both performance and power consumption must be considered to reduce the maintenance cost for quality of service guarantees. This paper proposes efficient and effective power management schemes for heterogeneous clusters. Distinct from existing heuristic approaches, we propose power management schemes with approximation factor guarantees, compared to the optimal power management. Our greedy power management schemes have 1.5-approximation or 2-approximation guarantees depending on the complexity. We also propose dynamic-programming approach which can trade the quality of the resulting solutions with different time/space complexity. Simulation results wrt different power consumption models show that the proposed schemes are effective for the minimization of the power consumption for large scale clusters.},
}

@inproceedings { DBLP:conf/emsoft/KumarCT11,
  author = {Kumar, Pratyush and Chen, Jian-Jia and Thiele, Lothar},
  title = {Demand bound server: generalized resource reservation for hard real-time systems},
  booktitle = {Proceedings of the 11th International Conference on Embedded Software, EMSOFT 2011, part of the Seventh Embedded Systems Week, ESWeek 2011, Taipei, Taiwan, October 9-14, 2011},
  date-modified = {2015-08-27 13:30:37 +0000},
  year = {2011},
  bdsk-url-1 = {http://doi.acm.org/10.1145/2038642.2038679},
  pages = {233-242},
  url = {http://doi.acm.org/10.1145/2038642.2038679},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Servers have been proposed to implement resource reservations on shared resources. Such reservations isolate the temporal behavior of tasks sharing the shared resources, thereby providing performance guarantees to tasks independent of other tasks. In existing work, resource reservation has been synonymous to utilization (also called bandwidth) on the resource, i.e., we can reserve only a constant fraction of the resource utilization via a server. Such reservation schemes are not suited to serve interrupt-like tasks: tasks that occur seldom but require quick service or tasks with jitter. With this motivation, we present a generalized server algorithm, called Demand Bound Server (DBS), whose offered service is characterized by the demand bound function (dbf) of the task it serves. We show that schedulability of DBS tightly follows that of EDF, and if schedulable a DBS provides a performance guarantee as requested by the dbf of the task. We present an implementation of DBS when the dbf is a shifted-periodic curve and characterize its overhead. We also present efficient composition operations on DBS that widen the class of implemented servers to tightly serve tasks arising in most practical settings.},
}

@inproceedings { DBLP:conf/codes/LampkaHC11,
  author = {Lampka, Kai and Huang, Kai and Chen, Jian-Jia},
  title = {Dynamic counters and the efficient and effective online power management of embedded real-time systems},
  booktitle = {Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2011, part of ESWeek '11 Seventh Embedded Systems Week, Taipei, Taiwan, 9-14 October, 2011},
  date-modified = {2015-08-27 13:30:40 +0000},
  year = {2011},
  bdsk-url-1 = {http://doi.acm.org/10.1145/2039370.2039412},
  pages = {267-276},
  url = {http://doi.acm.org/10.1145/2039370.2039412},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy consumption has become an important issue for modern embedded systems. This is because, one does not only like to deploy high-performance systems and provide guaranteed services, but also request system deployments to last as long as possible. With online dynamic power management (DPM), one adaptively changes the system's power mode, i.e., schedules when to turn on and off on-the-fly, to achieve energy savings. This paper introduces dynamic counters and discusses their usage in the context of (online) DPM in a setting where systems have to fulfill hard real-time requirements. The proposed scheme enables one to conservatively bound the future workload and thereby to safely schedule on- and off-periods of devices. Simulation results indicate that the proposed technique is more efficient and more effective with respect to energy savings, compared to previous work.},
}

@inproceedings { DBLP:conf/rtcsa/HuangCT11,
  author = {Huang, Kai and Chen, Jian-Jia and Thiele, Lothar},
  title = {Energy-Efficient Scheduling Algorithms for Periodic Power Management for Real-Time Event Streams},
  booktitle = {17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011, Toyama, Japan, August 28-31, 2011, Volume 1},
  date-modified = {2015-08-27 13:30:43 +0000},
  year = {2011},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2011.62},
  pages = {83-92},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2011.62},
  keywords = {jj-old},
  confidential = {n},
  abstract = {As modern VLSI technology is scaling to the deep sub-micron domain, embedded systems face a power-efficiency problem, i.e., static power consumption caused by the leakage current. This paper explores how to use dynamic power management to reduce static power consumption while guaranteeing hard real-time properties. To tackle event arrivals with non-deterministic patterns, the arrival curve model is adopted to describe event arrivals in the interval domain. To reduce runtime overhead, periodic power management is investigated, which turns on and off a system with a fixed period. To reduce the timing complexity of computing such a periodic scheme, two algorithms, which are based on a linear-segmented representation of the arrival curve model, are proposed to trade the complexity with accuracy for energy reduction. We also present simulation results to demonstrate the effectiveness of our algorithms.},
}

@inproceedings { DBLP:conf/rtcsa/KumarCTSB11,
  author = {Kumar, Pratyush and Chen, Jian-Jia and Thiele, Lothar and Schranzhofer, Andreas and Buttazzo, Giorgio C.},
  title = {Real-Time Analysis of Servers for General Job Arrivals},
  booktitle = {17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011, Toyama, Japan, August 28-31, 2011, Volume 1},
  date-modified = {2015-08-27 13:30:54 +0000},
  year = {2011},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2011.80},
  pages = {251-258},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2011.80},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Several servers have been proposed to schedule streams of a periodic jobs in the presence of other periodic tasks. Standard schedulability analysis has been extended to consider such servers. However, not much attention has been laid on computing the worst-case delay suffered by a given stream of jobs when scheduled via a server. Such analysis is essential for using servers to schedule hard real-time tasks. We illustrate, with examples, that well established resource models, such as supply bound function and models from Real-Time Calculus, do not tightly characterize servers. In this work, we analyze the server algorithm of the Constant Bandwidth Server and compute a provably tight resource model of the server. The approach used enables us to differentiate between the soft and hard variants of the server. A similar approach can be used to characterize other servers, the final results for which are presented.},
}

@inproceedings { DBLP:conf/rtss/LiCXL11,
  author = {Li, Jianjun and Chen, Jian-Jia and Xiong, Ming and Li, Guohui},
  title = {Workload-Aware Partitioning for Maintaining Temporal Consistency upon Multiprocessor Platforms},
  booktitle = {Proceedings of the 32nd IEEE Real-Time Systems Symposium, RTSS 2011, Vienna, Austria, November 29 - December 2, 2011},
  date-modified = {2015-08-27 13:31:11 +0000},
  year = {2011},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2011.19},
  pages = {126-135},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2011.19},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Deriving deadlines and periods of update transactions for maintaining timeliness and data freshness has long been recognized as an important problem in real-time database research. Despite years of active research, the state of the art only focuses on uniprocessor systems. In this paper, we take a first step of studying the workload-aware temporal consistency maintenance problem upon multiprocessor platforms. We consider the problem of how to partition a set of update transactions to $m \ge 2$ processors to maintain the temporal consistency of real-time data objects under earliest deadline first (EDF) scheduling, while minimizing the total workload on $m$ processors. Firstly, we only consider the feasibility aspect of the problem by proposing a polynomial time partitioning scheme, Temporal Consistency Partitioning (TCP), and formally showing that the resource augmentation bound of TCP is $({3 - \frac{1}{m}})$. Secondly, we address the partition problem globally by proposing a polynomial time heuristic, Density factor Balancing Fit (DBF), where density factor balancing plays a major role in producing workload-efficient partitionings. Finally, we evaluate the feasibility and workload performances of DBF versus other heuristics with comparable quality experimentally.},
}

@inproceedings { DBLP:conf/rtss/ChenC11,
  author = {Chen, Jian-Jia and Chakraborty, Samarjit},
  title = {Resource Augmentation Bounds for Approximate Demand Bound Functions},
  booktitle = {Proceedings of the 32nd IEEE Real-Time Systems Symposium, RTSS 2011, Vienna, Austria, November 29 - December 2, 2011},
  date-modified = {2015-08-27 13:30:57 +0000},
  year = {2011},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2011.32},
  pages = {272-281},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2011.32},
  keywords = {jj-old},
  confidential = {n},
  abstract = {In recent work, approximation of the demand bound function for a sporadic task uses a linear approximation when the interval length of interest is larger than the relative deadline of the task. Such an approximation leads to a factor 2 for resource augmentation under a naive analysis, i.e., if the schedulability test using this approximate demand bound function fails, the task set is not schedulable by slowing down the system to 50% of the original speed. In this paper we provide a tighter analysis of such an approach on uniprocessor systems and on identical multiprocessor systems with partitioned scheduling under the earliest-deadline-first strategy. For uniprocessor systems, we prove that the resource augmentation factor is at most $\frac{(2e-1)}{e}$, where e is the Euler number. For identical multiprocessor systems with M processors, with respect to resource augmentation, we show that deadline-monotonic partitioning with approximate demand bound functions leads to a factor $\frac{(3e-1)}/{e}-\frac{1}{M}$ for constrained-deadline task sets and a factor $3-\frac{1}{M}$ for arbitrary-deadline task sets, in which the best results known so far are $3-\frac{1}{M}$ for constrained-deadline ones and $4-\frac{2}{M}$ for arbitrary-deadline ones. Moreover, we also provide concrete input instances to show that the lower bound of resource augmentation factors for uniprocessor systems (identical multiprocessor systems under an arbitrary order of fitting and a large number of processors, respectively) under such approaches is 1.5 (2.5, respectively).},
}

@inproceedings { DBLP:conf/rtas/SchranzhoferPCTC11,
  author = {Schranzhofer, Andreas and Pellizzoni, Rodolfo and Chen, Jian-Jia and Thiele, Lothar and Caccamo, Marco},
  title = {Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters},
  booktitle = {17th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2011, Chicago, Illinois, USA, 11-14 April 2011},
  date-modified = {2015-08-27 13:31:06 +0000},
  year = {2011},
  bdsk-url-1 = {http://dx.doi.org/10.1109/RTAS.2011.28},
  pages = {213-222},
  url = {http://dx.doi.org/10.1109/RTAS.2011.28},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Modern multiprocessor and multicore architectures adopt shared resources to meet increased performance requirements. Adaptive arbiters, such as FlexRay, have been adopted to grant access to shared resources. While increasing the performance, timing analysis is more challenging with this kind of arbiter. This paper considers real-time tasks that are composed of super blocks, while super blocks themselves are composed of phases. Phases are characterized by their worst-case computation time on their processing element and their worst-case number of access requests to a shared resource. Resource accesses, such as access to caches or scratchpad memory, are synchronous and cause the processing element to stall until the access is served. Based on dynamic programming, we develop an algorithm that safely derives an upper-bound of the worst-case response time of a phase. The worst-case response time of a task can then be determined for both sequential or time-triggered execution of super blocks. Experimental results are conducted for a real-world application.},
}

@inproceedings { DBLP:conf/date/RaiYBCT11,
  author = {Rai, Devendra and Yang, Hoeseok and Bacivarov, Iuliana and Chen, Jian-Jia and Thiele, Lothar},
  title = {Worst-case temperature analysis for real-time systems},
  booktitle = {Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011},
  date-modified = {2015-08-27 13:31:15 +0000},
  year = {2011},
  bdsk-url-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5763104},
  pages = {631-636},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5763104},
  keywords = {jj-old},
  confidential = {n},
  abstract = {With the evolution of today's semiconductor technology, chip temperature increases rapidly mainly due to the growth in power density. For modern embedded real-time systems, it is crucial to estimate maximal temperatures in order to take mapping or other design decisions to avoid burnout, and still be able to guarantee meeting real-time constraints. This paper provides answers to the question: When work-conserving scheduling algorithms, such as earliest-deadline-first (EDF), rate-monotonie (RM), deadline-monotonic (DM), are applied, what is the worst-case peak temperature of a real-time embedded system under all possible scenarios of task executions? We propose an analytic framework, which considers a general event model based on network and real-time calculus. This analysis framework has the capability to handle a broad range of uncertainties in terms of task execution times, task invocation periods, and jitter in task arrivals. Simulations show that our framework is a cornerstone to design real-time systems that have guarantees on both schedulability and maximal temperatures.},
}

@inproceedings { DBLP:conf/sac/ChenT10,
  author = {Chen, Jian-Jia and Thiele, Lothar},
  title = {Energy-efficient scheduling on homogeneous multiprocessor platforms},
  booktitle = {Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010},
  date-modified = {2015-08-27 13:30:02 +0000},
  year = {2010},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1774088.1774198},
  pages = {542-549},
  url = {http://doi.acm.org/10.1145/1774088.1774198},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Low-power and energy-efficient system implementations have become very important design issues to extend operation duration or cut power bills. To balance the energy consumption resulting from the dynamic power consumption and the static power consumption, the concept of critical speed has been adopted widely in the literature. Most scheduling algorithms for such systems assume that the critical speed is the lowest speed for scheduling and then perform job/task procrastination to turn the processor(s) to the dormant mode when there is no job for execution. This paper shows that the critical speed might be too optimistic and turning the processor(s) to the dormant mode might be energy-inefficient. By allowing tasks to run at lower speeds than the critical speed, in this paper, a new approximation algorithm is developed for homogeneous multiprocessor systems with a 1.21-approximation factor, which significantly improves the state-of-the-art approximation algorithm with a 1.667-approximation factor. Performance evaluation shows the effectiveness of the proposed algorithm with comparison to the state-of-the-art approximation algorithm. Our algorithm can reduce the energy consumption by at most 15\% in our simulations.},
}

@inproceedings { DBLP:conf/dac/SchranzhoferPCTC10,
  author = {Schranzhofer, Andreas and Pellizzoni, Rodolfo and Chen, Jian-Jia and Thiele, Lothar and Caccamo, Marco},
  title = {Worst-case response time analysis of resource access models in multi-core systems},
  booktitle = {Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010},
  date-modified = {2015-08-27 13:30:28 +0000},
  year = {2010},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1837274.1837359},
  pages = {332-337},
  url = {http://doi.acm.org/10.1145/1837274.1837359},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Multi-processor and multi-core systems are becoming increasingly important in time critical systems. Shared resources, such as shared memory or communication buses are used to share data and read sensors. We consider real-time tasks constituted by superblocks, which can be executed sequentially or by a time triggered static schedule. Three models to access shared resources are explored: (1) the dedicated access model, in which accesses happen only in dedicated phases, (2) the general access model, in which accesses could happen at anytime, and (3) the hybrid access model, combining the dedicated and general access model. For resource access based on a Time Division Multiple Access (TDMA) protocol, we analyze the worst-case completion time for a superblock, derive worst-case response times for tasks and obtain the relation of schedulability between different models. We conclude with proposing the dedicated sequential model as the model of choice for time critical resource sharing multi-processor/multi-core systems.},
}

@inproceedings { DBLP:conf/islped/ParkCSKYC10,
  author = {Park, Sangyoung and Chen, Jian-Jia and Shin, Donghwa and Kim, Younghyun and Yang, Chia-Lin and Chang, Naehyuck},
  title = {Dynamic thermal management for networked embedded systems under harsh ambient temperature variation},
  booktitle = {Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010},
  date-modified = {2015-08-27 13:29:49 +0000},
  year = {2010},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1840845.1840905},
  pages = {289-294},
  url = {http://doi.acm.org/10.1145/1840845.1840905},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Modern vehicle electronics control units (ECUs) are getting rapidly complicated because of active safety and semi-autonomous driving controls, such as electric stability program (ESP) and adaptive cruise control (ACC). Furthermore, the operational environment of ECUs is extremely harsh, especially in terms of an ambient temperature well exceeding 100$\,^{\circ}$C, which causes a very small temperature headroom. Thus, ECUs require a careful temperature management and high performance at the same time. This paper introduces a dynamic thermal management (DTM) mechanism for networked embedded systems for vehicle ECUs. We exploit a fact that the ambient temperature of each ECU is different and also variable by the temperature of the associated unit while previous DTM considers a fixed ambient temperature as a given constant. We propose a new DTM that controls the rates of tasks with computation migration through the vehicle-area-network to maximize the minimum rate of tasks, which in turn enhances the quality of control and increases the maximum safe vehicle speed. We found that the ambient temperature of each ECU has different behavior for a particular operating condition, and suggest to use a proactive computation migration. We demonstrate dramatic improvement in die temperature control accuracy and average of 12.25\% improvements in overall quality of control over distributed reactive DTM for our example cases.},
}

@inproceedings { DBLP:conf/ecrts/WangCLL10,
  author = {Wang, Shengquan and Chen, Jian-Jia and Liu, Jun and Liu, Xue},
  title = {Power Saving Design for Servers under Response Time Constraint},
  booktitle = {22nd Euromicro Conference on Real-Time Systems, ECRTS 2010, Brussels, Belgium, July 6-9, 2010},
  date-modified = {2015-08-27 13:30:12 +0000},
  year = {2010},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/ECRTS.2010.31},
  pages = {123-132},
  url = {http://doi.ieeecomputersociety.org/10.1109/ECRTS.2010.31},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Reducing the power consumption while maintaining the response time constraint has been an important goal in server system design. One of the techniques widely explored in the literature to achieve this goal is Dynamic Voltage Scaling (DVS). However, DVS is not efficient in modern systems where the overall power consumption includes a large portion of static power consumption. In this paper, we aim to reduce the static power consumption by Dynamic Power Management (DPM) with sleep model in addition to DVS. We propose a smart PowerSleep power-saving scheme, where a procrastination technique is adopted to carefully aggregate jobs to reduce the overhead of transitions in and out of the sleep mode. We also observe that PowerSleep might not always be a good choice due to the mode transition overhead when the server utilization is high, where instead we use PowerIdle power-saving scheme with DVS only. By modeling the system with M/G/1/PS queuing model and further extensions, we present how to minimize the mean power consumption of the server under the given mean response time constraint for both power-saving schemes. Simulation results show that our smart PowerSleep scheme significantly outperforms the simple power saving scheme which adopts sleep mode.},
}

@inproceedings { DBLP:conf/rtas/SchranzhoferCT10,
  author = {Schranzhofer, Andreas and Chen, Jian-Jia and Thiele, Lothar},
  title = {Timing Analysis for TDMA Arbitration in Resource Sharing Systems},
  booktitle = {16th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2010, Stockholm, Sweden, April 12-15, 2010},
  date-modified = {2015-08-27 13:30:22 +0000},
  year = {2010},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2010.24},
  pages = {215-224},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2010.24},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Modern computing systems have adopted multicore architectures and multiprocessor systems on chip (MPSoCs) for accommodating the increasing demand on computation power. However, performance boosting is constrained by shared resources, such as buses, main memory, DMA, etc.This paper analyzes the worst-case completion (response) time for real-time tasks when time division multiple access (TDMA) policies are applied for resource arbitration.Real-time tasks execute periodically on a processing element and are constituted by sequential superblocks. A superblock is characterized by its accesses to a shared resource and its computation time. We explore three models of accessing shared resources: (1)dedicated access model, in which accesses happen only at the beginning and the end of a superblock, (2) general access model, in which accesses could happen anytime during the execution of a superblock, and (3) hybrid access model, which combines the dedicated and general access models. We present a framework to analyze the worst-case completion time of real-time tasks (superblocks) under these three access models, for a given TDMA arbiter. We compare the timing analysis of the three proposed models for a real-world application.},
}

@inproceedings { DBLP:conf/rtcsa/PerathonerTC10,
  author = {Perathoner, Simon and Thiele, Lothar and Chen, Jian-Jia},
  title = {Energy-Efficient Static Priority and Speed Assignment for Real-Time Tasks with Non-deterministic Release Times},
  booktitle = {16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2010, Macau, SAR, China, 23-25 August 2010},
  date-modified = {2015-08-27 13:30:09 +0000},
  year = {2010},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2010.9},
  pages = {173-182},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2010.9},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Dynamic Voltage Scaling (DVS) has been widely used for decreasing the dynamic power dissipation of processors. For real-time systems, DVS techniques have been developed that permit to meet the timing constraints of multiple real-time tasks and at the same time reduce the overall dynamic energy consumption. Known methods for static priority DVS scheduling are, however, either restricted to simple periodic/sporadic task release patterns or presume full a priori knowledge of task release times. Moreover, none of the present approaches considers the optimization of task priorities for reducing the energy consumption. In this paper we explore how to determine the static priorities and individual execution speeds (supply voltages) of multiple tasks with non-deterministic release times bounded by arrival curves such that the energy consumption is reduced and the real-time constraints are met. The result are different heuristics for the design of DVS-based real-time systems with static priorities. We show that the proposed methodology leads to energy-efficient system designs and demonstrate the applicability of the approach by means of experiments.},
}

@inproceedings { DBLP:conf/sutc/HasenfratzMMCT10,
  author = {Hasenfratz, David and Meier, Andreas and Moser, Clemens and Chen, Jian-Jia and Thiele, Lothar},
  title = {Analysis, Comparison, and Optimization of Routing Protocols for Energy Harvesting Wireless Sensor Networks},
  booktitle = {IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing, SUTC 2010 and IEEE International Workshop on Ubiquitous and Mobile Computing, UMC 2010, 7-9 June 2010, Newport Beach, California, USA},
  date-modified = {2015-08-27 13},
  year = {2010},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/SUTC.2010.35},
  pages = {19-26},
  url = {http://doi.ieeecomputersociety.org/10.1109/SUTC.2010.35},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy harvesting has been steadily gaining interest in the wireless sensor network community. Instead of minimizing the energy consumption and maximizing a network's operational time, the main challenge in energy harvesting sensor networks is to maximize the utility of the application subject to the harvested energy. One major challenge is to maximize the data delivery rates by exploiting the spatial variations of environmental energy. While there exists a multiplicity of energy-aware routing protocols for sensor networks without energy harvesting capabilities, only a small number of routing protocols have been published which explicitly account for energy harvesting. In this paper, we analyze and compare three state-of-the-art routing algorithms. While the original algorithms assume an idealized medium access control (MAC), a lossless wireless channel and global knowledge, we show that these assumptions lead to delusive results. We detail these findings by showing the influence of a low-power MAC protocol, a realistic wireless channel and the protocol overhead. Moreover, we show how to optimize the parameters of the MAC protocol for a given network configuration. By conducting various evaluations, we identify that our modified version of the R-MPRT algorithm outperforms the evaluated algorithms in scenarios where little energy is harvested from the environment.},
}

@inproceedings { DBLP:conf/aspdac/SchranzhoferCST10,
  author = {Schranzhofer, Andreas and Chen, Jian-Jia and Santinelli, Luca and Thiele, Lothar},
  title = {Dynamic and adaptive allocation of applications on MPSoC platforms},
  booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010},
  date-modified = {2015-08-27 13:29:41 +0000},
  year = {2010},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ASPDAC.2010.5419679},
  pages = {885-890},
  url = {http://dx.doi.org/10.1109/ASPDAC.2010.5419679},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Multi-Processor Systems-on-Chip (MPSoC) are an increasingly important design paradigm not only for mobile embedded systems but also for industrial applications such as automotive and avionic systems. Such systems typically execute multiple concurrent applications, with different execution modes. Modes define differences in functionality and computational resource demands and are assigned with an execution probability. We propose a dynamic mapping approach to maintain low power consumption over the system lifetime. Mapping templates for different application modes and execution probabilities are computed offline and stored on the system. At runtime a manager monitors the system and chooses an appropriate pre-computed template. Experiments show that our approach outperforms global static mapping approaches up to 45\%.},
}

@inproceedings { DBLP:conf/aspdac/MoserCT10,
  author = {Moser, Clemens and Chen, Jian-Jia and Thiele, Lothar},
  title = {Dynamic power management in environmentally powered systems},
  booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010},
  date-modified = {2015-08-27 13:29:43 +0000},
  year = {2010},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ASPDAC.2010.5419916},
  pages = {81-88},
  url = {http://dx.doi.org/10.1109/ASPDAC.2010.5419916},
  keywords = {jj-old},
  confidential = {n},
  abstract = {In this paper a framework for energy management in energy harvesting embedded systems is presented. As a possible example scenario, we focus on wireless sensor nodes which are powered by solar cells. We demonstrate that classical power management solutions have to be reconceived and/or new problems arise if perpetual operation of the system is required. In particular, we provide a set of algorithms and methods for different application scenarios, including real-time scheduling, application rate control as well as reward maximization. The goal is to optimize the performance of the application subject to given energy constraints. Our methods optimize the system performance which allows the usage of, e.g., smaller solar cells and smaller batteries. Our theoretical results are supported by simulations using long-term measurements of solar energy in an outdoor environment. Furthermore, to demonstrate the practical relevance of our approaches, we measured the implementation overhead of our algorithms on real sensor nodes.},
}

@inproceedings { DBLP:conf/aspdac/HuangSCTB10,
  author = {Huang, Kai and Santinelli, Luca and Chen, Jian-Jia and Thiele, Lothar and Buttazzo, Giorgio C.},
  title = {Adaptive power management for real-time event streams},
  booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010},
  date-modified = {2015-08-27 13:29:24 +0000},
  year = {2010},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ASPDAC.2010.5419928},
  pages = {7-12},
  url = {http://dx.doi.org/10.1109/ASPDAC.2010.5419928},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Dynamic power management has become essential for battery-driven embedded systems. This paper explores how to efficiently and effectively reduce the energy consumption of a device (system) for serving multiple event streams. Considering two different preemptive scheduling, i.e., earliest deadline first and fixed priority, we propose new method to adaptively control the power mode of the device according to historical arrivals of events. Our method can not only tackle arbitrary event arrivals but also provide hard real-time guarantees with respect to both timing and backlog constraints. Simulation results are presented as well to demonstrate the effectiveness of our approach.},
}

@inproceedings { DBLP:conf/iccad/PerathonerLSTC10,
  author = {Perathoner, Simon and Lampka, Kai and Stoimenov, Nikolay and Thiele, Lothar and Chen, Jian-Jia},
  title = {Combining optimistic and pessimistic DVS scheduling: An adaptive scheme and analysis},
  booktitle = {2010 International Conference on Computer-Aided Design (ICCAD'10), November 7-11, 2010, San Jose, CA, USA},
  date-modified = {2015-08-27 13:29:34 +0000},
  year = {2010},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ICCAD.2010.5654109},
  pages = {131-138},
  url = {http://dx.doi.org/10.1109/ICCAD.2010.5654109},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Performance boosting of modern computing systems is constrained by the chip/circuit power dissipation. Dynamic voltage scaling (DVS) has been applied for reducing the energy consumption by dynamically changing the supply voltage. One can optimistically apply greedy online DVS scheduling algorithms by considering only the events that have arrived in the system. However, this might require a speed that is beyond a system's capability. Alternatively, one can pessimistically use a conservative speed to ensure timing guarantees, which might consume an excessive amount of energy as events might be processed faster than necessary. This paper presents an adaptive scheme that combines these two strategies for the scheduling of arbitrary event streams. The proposed adaptive DVS scheduler chooses the execution speed dynamically as long as it is below a certain threshold. Once the speed exceeds this threshold, the proposed scheduler operates at a constant (pessimistic) speed for guaranteeing the feasibility. The computation of the threshold speed is, however, not straight-forward. For deriving it, we make use of a framework based on timed model checking because the scheduler is strongly state-dependent. The resulting analysis framework allows to obtain the threshold speed for the proposed adaptive DVS scheduling algorithm such that both timing and speed constraints are guaranteed to be met and at the same time an energy-efficient execution is ensured.},
}

@inproceedings { DBLP:conf/isqed/WangC10,
  author = {Wang, Shengquan and Chen, Jian-Jia},
  title = {Thermal-aware lifetime reliability in multicore systems},
  booktitle = {11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, US},
  date-modified = {2015-08-27 13:30:19 +0000},
  year = {2010},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ISQED.2010.5450548},
  pages = {399-405},
  url = {http://dx.doi.org/10.1109/ISQED.2010.5450548},
  keywords = {jj-old},
  confidential = {n},
  abstract = {As the power density of modern electronic circuits increases dramatically, systems are prone to overheating. High temperatures not only raise packaging costs, degrade system performance, and increase leakage power consumption, but also reduce the system reliability. Due to many limits in single core design including the performance and the power density, the microprocessor industry has switched their attentions to multicore design to enable the scaling of performance. Thermal effects on multicore systems are still prominent issues. One typical thermal effect is the thermal-aware lifetime reliability, which has become a serious concern. In this paper, we address the issue on how to maximize the lifetime of multicore systems while maintaining a given aggregate processor speed. By applying sequential quadratic programming, we present how to derive the ideal speed for each core to maximize the system lifetime. We perform experiments on several multi-core platforms, which show that the proposed method can significantly outperform the existing approaches by minimizing the peak temperature of the system.},
}

@inproceedings { DBLP:conf/kit/Chen10,
  author = {Chen, Jian-Jia},
  title = {Designing Energy-Efficient, Predictable, and Reliable Real-Time and Embedded Systems},
  booktitle = {Emerging Research Directions in Computer Science, Karlsruhe, Germany, July 26-27, 2010. Proceedings - KIT Nachwuchswissenschaftler-Symposium, Contributions from the Young Informatics Faculty in Karlsruhe},
  date-modified = {2015-08-27 13:29:38 +0000},
  year = {2010},
  bdsk-url-1 = {http://dx.doi.org/10.5445/KSP/1000017357},
  pages = {37-44},
  url = {http://dx.doi.org/10.5445/KSP/1000017357},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Embedded systems have been widely adopted and deployed in many application domains, while the average or worst-case response time in many applications is a non-functional but important requirement. For best-effort systems, such as telecommunication devices or hand-held applications, the average response time is expected to be short to maintain the good reactivity and good dependability. For critical-control systems, such as automotive controllers or automated aircraft landing systems, high reactivity and high dependability must be ensured by the worst-case response time guarantee to maintain the safety and the stability of the systems. There are many challenges for designing embedded systems, to satisfy functional properties, such as compilers, embedded program- ming languages, etc., and non-functional properties, such as energy re- duction, reliability, timing predictability, etc. The chair of Micro Hard- ware Technologies for Automation focuses on the design and analysis of the non-functional properties for real-time embedded systems. This arti- cle presents current research and future research directions, in the chair, for designing energy-efficient, predictable, and reliable real-time and em- bedded systems.},
}

@inproceedings { DBLP:conf/date/PellizzoniSCCT10,
  author = {Pellizzoni, Rodolfo and Schranzhofer, Andreas and Chen, Jian-Jia and Caccamo, Marco and Thiele, Lothar},
  title = {Worst case delay analysis for memory interference in multicore systems},
  booktitle = {Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010},
  date-modified = {2015-08-27 13:30:25 +0000},
  year = {2010},
  bdsk-url-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5456952},
  pages = {741-746},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5456952},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access to main memory can greatly increase a task's WCET. In this paper, we introduce an analysis methodology that computes upper bounds to task delay due to memory contention. First, an arrival curve is derived for each core representing the maximum memory traffic produced by all tasks executed on it. Arrival curves are then combined with a representation of the cache behavior for the task under analysis to generate a delay bound. Based on the computed delay, we show how tasks can be feasibly scheduled according to assigned time slots on each core.},
}

@inproceedings { DBLP:conf/date/YangCTK10,
  author = {Yang, Chuan-Yue and Chen, Jian-Jia and Thiele, Lothar and Kuo, Tei-Wei},
  title = {Energy-efficient real-time task scheduling with temperature-dependent leakage},
  booktitle = {Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010},
  date-modified = {2015-08-27 13:29:58 +0000},
  year = {2010},
  bdsk-url-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5457243},
  pages = {9-14},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5457243},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Leakage power consumption contributes significantly to the overall power dissipation for systems that are manufactured in advanced deep sub-micron technology. Different from many previous results, this paper explores leakage-aware energy-efficient scheduling if leakage power consumption depends on temperature. We propose a pattern-based approach which divides a given time horizon into several time segments with the same length, where the processor is in the active (dormant, respectively) mode for a fixed amount of time at the beginning (end, respectively) of each time segment. Computation is advanced in the active mode, whereas the dormant mode helps reduce the temperature via cooling as well as the leakage power consumption. Since the pattern-based approach leads to a steady state with an equilibrium temperature, we develop a procedure to find the optimal pattern whose energy consumption in steady state is the minimum. Compared to existing work, our approach is more effective, has less run-time scheduling overhead, and requires only a simple scheduler to control the system mode periodically. The paper contains extensive simulation results which validate the new models and methods.},
}

@inproceedings { DBLP:conf/sac/MoserCT09,
  author = {Moser, Clemens and Chen, Jian-Jia and Thiele, Lothar},
  title = {Optimal service level allocation in environmentally powered embedded systems},
  booktitle = {Proceedings of the 2009 ACM Symposium on Applied Computing (SAC), Honolulu, Hawaii, USA, March 9-12, 2009},
  date-modified = {2015-08-27 13:27:14 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1529282.1529653},
  pages = {1650-1657},
  url = {http://doi.acm.org/10.1145/1529282.1529653},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy management is a critical concern in the design of embedded systems to prolong the lifetime or to maximize the performance under energy constraints. In particular, the emerging embedded systems with renewable energy sources rise new problems and trigger the revision of conventional energy management. If, e.g., the size of a solar cell limits the available power/energy of an electronic device, decisions like when to provide which service have to be made in order to satisfy the needs of the user as well as possible. In this paper, we explore how to maximize the system reward of diverse applications for an energy harvesting system. By utilizing the notion of rewards to express the different priorities of services, we answer the fundamental question of how to optimize the use of energy provided by a scarce and time-varying environmental source. For this purpose, we provide algorithms to optimally adjust service parameters dynamically. Our work is supported by simulation results which are based on long-term measurements of the power generated by real solar cells. Furthermore, we demonstrate how to dimension the embedded system, e.g., the battery capacity and elaborate on implementation details which are of practical importance.},
}

@inproceedings { DBLP:conf/islped/MoserCT09,
  author = {Moser, Clemens and Chen, Jian-Jia and Thiele, Lothar},
  title = {Power management in energy harvesting embedded systems with discrete service levels},
  booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
  date-modified = {2015-08-27 13:27:21 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1594233.1594338},
  pages = {413-418},
  url = {http://doi.acm.org/10.1145/1594233.1594338},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Power management has been a critical issue in the design of embedded systems due to the limited power supply. To prolong the lifetime, energy minimization has been studied under performance constraints in the past decade. The emerging embedded systems with the capability to harvest energy from the environment have recently triggered the revision of power management to improve the quality of service dynamically. As the available power/energy of an electronic device changes over time and is limited by many environmental factors, the system has to decide when to change to which service level to provide better quality of service without wasting the harvested energy. In this paper, we explore how to maximize the quality of service, in terms of system rewards, of a periodic application with discrete levels in an energy harvesting system. To decide service levels in a time horizon, this paper presents algorithms to derive optimal solutions if the future harvested energy is known. In addition, we present efficient algorithms to derive near-optimal solutions approximately. Our work is supported by simulation results which are based on long-term measurements of the power generated by real solar cells.},
}

@inproceedings { DBLP:conf/codes/YangCK09,
  author = {Yang, Chuan-Yue and Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Energy-efficiency for multiframe real-time tasks on a dynamic voltage scaling processor},
  booktitle = {Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 200},
  date-modified = {2015-08-27 13:26:58 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1629435.1629465},
  pages = {211-220},
  url = {http://doi.acm.org/10.1145/1629435.1629465},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-aware design for electronic systems has been an important issue in hardware and software implementations. Dynamic voltage scaling (DVS) techniques have been adopted to effectively trade the performance for the energy consumption. However, most existing research for energy-efficient design in DVS systems with realtime constraints focuses on tasks with worst-case execution times. Once a task instance completes earlier than its worst-case estimation, the unused slacks can be used for slowing down to reduce the energy consumption. This paper explores how to efficiently and effectively minimize the energy consumption to schedule a set of periodic real-time tasks with the multiframe property, in which the execution times of task instances are characterized by a vector of elements that are repeated. This paper proposes two types of approaches: (1) the task-based approach and (2) the frame-based approach. The task-based approach allocates the same time length for the executions of task instances belonging to the same task. The frame-based approach can reduce the energy consumption further by assigning an execution speed to each task frame. For on-line use, the scheduling overhead for speed determination is constant in both types of the proposed approaches. Simulations show that our proposed approaches sacrifice some optimality in terms of energy savings, compared to the optimal solutions, but require less space and less overhead for scheduling in the on-line (run-time) fashion.},
}

@inproceedings { DBLP:conf/etfa/YangCKT09,
  author = {Yang, Chuan-Yue and Chen, Jian-Jia and Kuo, Tei-Wei and Thiele, Lothar},
  title = {Energy Reduction Techniques for Systems with non-DVS Components},
  booktitle = {Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2009, September 22-25, 2008, Palma de Mallorca, Spain},
  date-modified = {2015-08-27 13:26:54 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/ETFA.2009.5347153},
  pages = {1-8},
  url = {http://doi.ieeecomputersociety.org/10.1109/ETFA.2009.5347153},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Dynamic voltage scaling (DVS) has been widely adopted to reduce the energy consumption resulting from the dynamic power of modern processors. However, while the leakage power resulting from the leakage current becomes significant, how to aggregate the idle time to turn processors to the sleep or dormant modes is crucial in reducing the overall energy consumption. Moreover, for systems with non-DVS components, the execution order of tasks also affects the system-wide energy consumption. With the consideration of the dynamic and leakage power of processors as well as the power consumption resulting from non-DVS components, this paper summarizes our work on energy-efficient real-time task scheduling for both uniprocessor and multiprocessor platforms through procrastination of task executions, preemption control, and proper task assignment.},
}

@inproceedings { DBLP:conf/isorc/WuC09,
  author = {Wu, Jun and Chen, Jian-Jia},
  title = {Real-Time Scheduling of Weighted Jobs with Multiple Feasible Intervals},
  booktitle = {2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC 2009, Tokyo, Japan, 17-20 March 2009},
  date-modified = {2015-08-27 13:27:31 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/ISORC.2009.38},
  pages = {143-147},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISORC.2009.38},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Time-critical jobs in many real-time applications have multiple feasible intervals. Such a job must be executed within one of its feasible intervals. In this paper, we are interested in maximizing the sum of the weights of the multiple feasible interval jobs that complete in time when jobs are associated with weights for its in-time completion. We develop heuristic algorithms that apply the least-earliest-completion-time-first (LECF) strategy as a schedulability test or apply variations of the LECF strategy with job evictions. The capability of our proposed algorithms is verified by a series of simulations.},
}

@inproceedings { DBLP:conf/mdm/TsaiCL09,
  author = {Tsai, Tzu-Chieh and Chen, Jian-Jia and Lo, Wen-Ching},
  title = {Design and Implementation of Mobile Personal Emotion Monitoring System},
  booktitle = {MDM 2009, Tenth International Conference on Mobile Data Management, Taipei, Taiwan, 18-20 May 2009},
  date-modified = {2015-08-27 13:26:48 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/MDM.2009.78},
  pages = {430-435},
  url = {http://doi.ieeecomputersociety.org/10.1109/MDM.2009.78},
  keywords = {jj-old},
  confidential = {n},
  abstract = {It is suggested that emotion plays a significant role in rational and intelligent behaviors. People behave emotions in different ways, and may not be noticeable through outside appearances. However, physiological information may reveal the clue for emotions. We proposed a mobile personal emotion monitoring system design, and proposed an adaptive algorithm that can help recognize user's emotion stateby using physiological sensors. We applied the dimensional analysis approach and adopted IAPS (International Affective Picture System) to manipulate psychological experiments. We also proposed an emotion recognition learning algorithm. It would extract each pattern of emotions from cross validation training and can further learn adaptively by feeding personalized testing data. We measured the learning rate of each subject which reveals incremental enhancement. Furthermore, we adopted a dimensional to discrete emotion transforming concept for validating the subjective rating. Compared to the experiment results of related works, our system outperforms both in dimensional and discrete analyses. Most importantly, the system is implemented based on wireless physiological sensors for mobile usage. This system can reflect the image of emotion states in order to provide on-line smart services.},
}

@inproceedings { DBLP:conf/rtas/SchranzhoferCT09,
  author = {Schranzhofer, Andreas and Chen, Jian-Jia and Thiele, Lothar},
  title = {Power-Aware Mapping of Probabilistic Applications onto Heterogeneous MPSoC Platforms},
  booktitle = {15th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2009, San Francisco, CA, USA, 13-16 April 2009},
  date-modified = {2015-08-27 13:27:24 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2009.24},
  pages = {151-160},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2009.24},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Multiprocessor SOC platforms have been adopted for a wide range of high performance applications. Task assignment and processing unit allocation are key steps in the design of predictable and efficient embedded systems. Provided that the probability distributions and mutual exclusion conditions for executing applications are known a priori, this paper explores the mapping of tasks onto processing units while minimizing the expected average power consumption. The underlying model considers static (leakage) and dynamic power. This study shows that deriving approximative solutions with a constant worst-case approximation factor in polynomial time is not achievable unless P = NP, even if a feasible task mapping is provided as an input. A polynomial-time heuristic algorithm is proposed that applies a multiple-step heuristic. Experimental results reveal the effectiveness of the proposed algorithm by comparing the derived solutions to the optimal ones, obtained via an integer linear program (ILP) specification.},
}

@inproceedings { DBLP:conf/rtas/ChenWT09,
  author = {Chen, Jian-Jia and Wang, Shengquan and Thiele, Lothar},
  title = {Proactive Speed Scheduling for Real-Time Tasks under Thermal Constraints},
  booktitle = {15th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2009, San Francisco, CA, USA, 13-16 April 200},
  date-modified = {2015-08-27 13:27:27 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2009.30},
  pages = {141-150},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2009.30},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Thermal management becomes a prominent issue in system design for both server systems and embedded systems. A system could fail if the peak temperature exceeds its thermal constraint. This research studies thermal-constrained scheduling for frame-based real-time tasks on a dynamic voltage/speed scaling system. Our objective is to design speed schedulers for real-time tasks by utilizing dynamic voltage/speed scaling to meet both timing and thermal constraints. Two approaches are proposed: One is based on the minimization of the response time under the thermal constraint, and the other is based on the minimization of the temperature under the timing constraint. We present detailed schedulability analysis for both proposed approaches. Our data show that our proposed proactive approaches outperform existing reactive ones.},
}

@inproceedings { DBLP:conf/rtas/FisherCWT09,
  author = {Fisher, Nathan and Chen, Jian-Jia and Wang, Shengquan and Thiele, Lothar},
  title = {Thermal-Aware Global Real-Time Scheduling on Multicore Systems},
  booktitle = {15th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2009, San Francisco, CA, USA, 13-16 April 2009},
  date-modified = {2015-08-27 13:27:37 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2009.34},
  pages = {131-140},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2009.34},
  keywords = {jj-old},
  confidential = {n},
  abstract = {As the power density of modern electronic circuits increases dramatically, systems are prone to overheating.},
}

@inproceedings { DBLP:conf/rtcsa/WangCST09,
  author = {Wang, Shengquan and Chen, Jian-Jia and Shi, Zhenjun and Thiele, Lothar},
  title = {Energy-Efficient Speed Scheduling for Real-Time Tasks under Thermal Constraints},
  booktitle = {15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009, Beijing, China, 24-26 August 2009},
  date-modified = {2015-08-27 13:27:02 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2009.29},
  pages = {201-209},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2009.29},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Thermal constraints have limited the performance improvement of modern computing systems in recent years. As a system could fail if the peak temperature exceeds its thermal constraint, overheating should be avoided while designing a system. Moreover, higher temperature also leads to higher leakage power consumption. This paper explores dynamic thermal management to minimize the energy consumption for a specified computing demand under the thermal constraint. We develop energy-efficient speed scheduling schemes for frame-based real-time tasks under thermal constraints. Experimental results reveal the effectiveness of the proposed scheme in terms of energy consumption in comparison with the reactive schemes in the literature.},
}

@inproceedings { DBLP:conf/rtcsa/ChenT09,
  author = {Chen, Jian-Jia and Thiele, Lothar},
  title = {Task Partitioning and Platform Synthesis for Energy Efficiency},
  booktitle = {15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2009, Beijing, China, 24-26 August 2009},
  date-modified = {2015-08-27 13:27:34 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2009.48},
  pages = {393-402},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2009.48},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-efficient and power-aware designs have played important roles in modern computing systems to reduce the power bills for server systems or prolong the lifetime of embedded devices. Moreover, systems with multiple heterogeneous processing units have been widely adopted to enhance the computing capability or reduce the power consumption. This work explores how to synthesize a heterogeneous multiprocessor platform or select processing units with the partitioning of real-time tasks so that the energy consumption is minimized. Given a set of processing unit types, characterized by the power consumption for maintaining activeness and executing jobs, this paper proposes an efficient and effective algorithm to allocate processing units with energy-efficient task partitioning. We show that the algorithm is with a $(1+\ln n)$-approximation factor, in worst cases, for processing unit types with a variety of power consumption models, where $n$ is the number of tasks. The approximation factor is asymptotically optimal for polynomial-time approximation algorithms unless ${\cal P}={\cal NP}$. Experimental results show that the proposed algorithm is effective for energy consumption minimization.},
}

@inproceedings { DBLP:conf/rtss/ChenST09,
  author = {Chen, Jian-Jia and Stoimenov, Nikolay and Thiele, Lothar},
  title = {Feasibility Analysis of On-Line DVS Algorithms for Scheduling Arbitrary Event Streams},
  booktitle = {Proceedings of the 30th IEEE Real-Time Systems Symposium, RTSS 2009, Washington, DC, USA, 1-4 December 2009},
  date-modified = {2015-08-27 13:27:06 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2009.21},
  pages = {261-270},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2009.21},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Performance boosting of modern computing systems has been constrained by the significant chip/circuit power dissipation. Dynamic voltage scaling (DVS) has been applied in the past decade for reducing the energy consumption by dynamically changing the supply voltage. On-line scheduling algorithms for DVS systems usually guarantee the real-time constraints of the system based on the condition that they can select any system speed that is sufficiently high to allow processing of all events within their deadlines. However, practical systems have a maximum available system speed and the feasibility of using on-line DVS algorithms needs to be verified during design time, i.e., they will never require during runtime a speed higher than the maximum available. This paper presents feasibility analysis of two on-line DVS algorithms that can compute in advance an upper bound on the system speed that these algorithms may require given that there is a single input event stream described by the worst-case event arrivals in interval domain. Moreover, we also present new results on the competitive ratios of the resulting schedules for energy consumption minimization with comparison to the off-line optimal solutions to show the effectiveness of the two algorithms. At the end, the performance of the different algorithms is evaluated.},
}

@inproceedings { DBLP:conf/rtss/HuangSCTB09,
  author = {Huang, Kai and Santinelli, Luca and Chen, Jian-Jia and Thiele, Lothar and Buttazzo, Giorgio C.},
  title = {Adaptive Dynamic Power Management for Hard Real-Time Systems},
  booktitle = {Proceedings of the 30th IEEE Real-Time Systems Symposium, RTSS 2009, Washington, DC, USA, 1-4 December 200},
  date-modified = {2015-08-27 13:26:42 +0000},
  year = {2009},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2009.25},
  pages = {23-32},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2009.25},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Power dissipation has constrained the performance boosting of modern computer systems in the past decade. Dynamic power management has been widely applied to change the system (or device) state dynamically to reduce the power consumption. This paper explores how to effectively reduce the energy consumption to handle event streams with hard real-time guarantees. We adopt Real-Time Calculus to describe the event arrival and resource service by arrival curves and service curves in the interval domain, respectively. We develop online algorithms to adaptively control the power mode of the device, postponing the processing of arrival events as late as possible. Profited from the worst-case interval-based abstraction, our algorithms can on one hand tackle arbitrary event arrivals (even with burstiness) and on the other hand guarantee hard real-time requirements in terms of both timing and backlog constraints. We also present simulation results to demonstrate the effectiveness of our algorithms.},
}

@inproceedings { DBLP:conf/qshine/RaoLCL09,
  author = {Rao, Lei and Liu, Xue and Chen, Jian-Jia and Liu, Wenyu},
  title = {Joint Optimization of System Lifetime and Network Performance for Real-Time Wireless Sensor Networks},
  booktitle = {Quality of Service in Heterogeneous Networks, 6th International ICST Conference on Heterogeneous Networking for Quality, Reliability, Security and Robustness, QShine 2009 and 3rd International Workshop on Advanced Architectures and Algorithms for Internet},
  year = {2009},
  bdsk-url-1 = {http://dx.doi.org/10.1007/978-3-642-10625-5_20},
  pages = {317-333},
  url = {http://dx.doi.org/10.1007/978-3-642-10625-5_20},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Maximizing the aggregate network utility and minimizing the network energy consumption are important but conflict goals in wireless sensor networks. Challenges arise due to the application-specific computing and communication resources constraints and end-to-end real-time constraints. This paper studies the tradeoff between energy consumption and network performance in Real-Time Wireless Sensor Networks (RTWSN) by investigating the interaction between the network performance optimization and network lifetime maximization problems. We address the tradeoff between these two conflict goals as a joint non-linear optimization problem. Based the solution of the optimization problem, we design an online distributed algorithm to achieve judicious tradeoff based on application-specific focus, while at the same time meeting real-time and resource constraints. Extensive simulation studies illustrate the efficiency and efficacy of the proposed algorithm.},
}

@inproceedings { DBLP:conf/cdc/HuangSCTB09,
  author = {Huang, Kai and Santinelli, Luca and Chen, Jian-Jia and Thiele, Lothar and Buttazzo, Giorgio C.},
  title = {Periodic power management schemes for real-time event streams},
  booktitle = {Proceedings of the 48th IEEE Conference on Decision and Control, CDC 2009, combined withe the 28th Chinese Control Conference, December 16-18, 2009, Shanghai, China},
  date-modified = {2015-08-27 13:27:18 +0000},
  year = {2009},
  bdsk-url-1 = {http://dx.doi.org/10.1109/CDC.2009.5400034},
  pages = {6224-6231},
  url = {http://dx.doi.org/10.1109/CDC.2009.5400034},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Power dissipation has constrained the performance boosting of modern computer systems in the past decade. Dynamic power management (DPM) has been implemented in many systems to change the system (or device) state dynamically to reduce the power consumption. This paper explores how to efficiently and effectively reduce the energy consumption to handle event streams with hard real-time or quality of service (QoS) guarantees. We adopt real-time calculus to describe the event arrival by arrival curves in the interval domain. To reduce the implementation overhead, we propose a periodic scheme to determine when to turn on/off the system (or device). This paper first presents two approaches to derive periodic scheme to cope with systems with only one event stream, in which one approach derives an optimal solution for periodic power management with higher complexity and the other derives approximated solutions with lower complexity. Then, extensions are proposed to deal with multiple event streams. Simulation results reveal the effectiveness of our approaches.},
}

@inproceedings { DBLP:conf/ipps/ChenST09,
  author = {Chen, Jian-Jia and Schranzhofer, Andreas and Thiele, Lothar},
  title = {Energy minimization for periodic real-time tasks on heterogeneous processing units},
  booktitle = {23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009},
  date-modified = {2015-08-27 13:26:52 +0000},
  year = {2009},
  bdsk-url-1 = {http://dx.doi.org/10.1109/IPDPS.2009.5161024},
  pages = {1-12},
  url = {http://dx.doi.org/10.1109/IPDPS.2009.5161024},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Adopting multiple processing units to enhance the computing capability or reduce the power consumption has been widely accepted for designing modern computing systems. Such configurations impose challenges on energy efficiency in hardware and software implementations. This work targets power-aware and energy-efficient task partitioning and processing unit allocation for periodic real-time tasks on a platform with a library of applicable processing unit types. Each processing unit type has its own power consumption characteristics for maintaining its activeness and executing jobs. This paper proposes polynomial-time algorithms for energy-aware task partitioning and processing unit allocation. The proposed algorithms first decide how to assign tasks onto processing unit types to minimize the energy consumption, and then allocate processing units to fit the demands. The proposed algorithms for systems without limitation on the allocated processing units are shown with an (m + 1)-approximation factor, where mis the number of the available processing unit types. For systems with limitation on the number of the allocated processing units, the proposed algorithm is shown with bounded resource augmentation on the limited number of allocated units. Experimental results show that the proposed algorithms are effective for the minimization of the overall energy consumption.},
}

@inproceedings { DBLP:conf/date/YangCKT09,
  author = {Yang, Chuan-Yue and Chen, Jian-Jia and Kuo, Tei-Wei and Thiele, Lothar},
  title = {An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems},
  booktitle = {Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009},
  date-modified = {2015-08-27 13:26:45 +0000},
  year = {2009},
  bdsk-url-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=5090609%7B%5C\&%7Darnumber=5090754%7B%5C\&%7Dcount=326%7B%5C\&%7Dindex=140},
  pages = {694-699},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=5090609{\\&}arnumber=5090754{\\&}count=326{\\&}index=140},
  keywords = {jj-old},
  confidential = {n},
  abstract = {As application complexity increases, modern embedded systems have adopted heterogeneous processing elements to enhance the computing capability or to reduce the power consumption. The heterogeneity has introduced challenges for energy efficiency in hardware and software implementations. This paper studies how to partition real-time tasks on a platform with heterogeneous processing elements (processors) so that the energy consumption can be minimized. The power consumption models considered in this paper are very general by assuming that the energy consumption with higher workload is larger than that with lower workload, which is true for many systems. We propose an approximation scheme to derive near-optimal solutions for different hardware configurations in energy/power consumption. When the number of processors is a constant, the scheme is a fully polynomial time approximation scheme (FPTAS) to derive a solution with energy consumption very close to the optimal energy consumption in polynomial-time/space complexity. Experimental results reveal that the proposed scheme is very effective in energy efficiency with comparison to the state-of-the-art algorithm.},
}

@inproceedings { DBLP:conf/sac/PerngCK08,
  author = {Perng, Nei-Chiung and Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {The minimization of hardware size in reconfigurable embedded platforms},
  booktitle = {Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008},
  date-modified = {2015-08-27 13:26:36 +0000},
  year = {2008},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1363686.1364041},
  pages = {1517-1522},
  url = {http://doi.acm.org/10.1145/1363686.1364041},
  keywords = {jj-old},
  confidential = {n},
  abstract = {To minimize the hardware fabrications in reconfigurable devices, this paper explores hardware synthesis to derive reconfiguration plans during the design time based on schedules derived by CAD tools, where a schedule includes the starting time, the execution time, and the intertask data transmissions for each task. We propose scheduling algorithms to derive optimal solutions for hardware descriptions with the same reconfiguration latency based on backward configuration and backward ordering strategies. For general cases, where a hardware description might be shared by tasks, we develop an algorithm based on a duplication merging strategy with performance evaluations. Our proposed algorithms could be applied after the hardware/software co-design procedures of task partitioning and scheduling to optimize the hardware requirements during the design time.},
}

@inproceedings { DBLP:conf/sac/Chen08,
  author = {Chen, Jian-Jia},
  title = {Expected energy consumption minimization in DVS systems with discrete frequencies},
  booktitle = {Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008},
  date-modified = {2015-08-27 13:26:24 +0000},
  year = {2008},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1363686.1364095},
  pages = {1720-1725},
  url = {http://doi.acm.org/10.1145/1363686.1364095},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-efficiency has been an important system issue in hardware and software designs to extend operation duration or out power bils. This research explores systems with probabilistic distribution on the execution time of real-time tasks for systems with discrete frequencies. Most previous studies consider DVS systems with continuous frequencies for the minimization of expected energy consumption under timing constraints. However, these approaches cannot guarantee the minimization of expected energy consumption when only discrete frequencies are available. This paper presents new approaches to minimize the expected energy consumption. By applying intra-task frequency scheduling, we develop an efficient algorithm to derive optimal frequency scheduling for a single task. The algorithm is then extended to cope with periodic real-time tasks with different power characteristics. With inter-task and intra-task frequency scheduling, we present a linear-programming approach to derive optimal solutions for frame-based real-time tasks and an on-line algorithm for periodic real-time tasks. Experimental results show that the proposed algorithms can effectively reduce the expected energy consumption.},
}

@inproceedings { DBLP:conf/islped/ChenT08,
  author = {Chen, Jian-Jia and Thiele, Lothar},
  title = {Expected system energy consumption minimization in leakage-aware DVS systems},
  booktitle = {Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008},
  date-modified = {2015-08-27 13:26:27 +0000},
  year = {2008},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1393921.1394006},
  pages = {315-320},
  url = {http://doi.acm.org/10.1145/1393921.1394006},
  keywords = {jj-old},
  confidential = {n},
  abstract = {The pursuit of energy efficiency is becoming more and more important in hardware and software designs. This research explores energy-efficient scheduling for a periodic real-time task with uncertain execution time in dynamic voltage scaling (DVS) systems with non-negligible leakage/static power consumption. Distinct from the assumption of non-reducible static power consumption in the literature, this paper considers the possibility to reduce it by turning a processor to a dormant mode. We propose an algorithm to derive an optimal frequency assignment to minimize the expected energy consumption without procrastination, while another extended algorithm is developed to apply procrastination scheduling for further energy reduction. Experimental results show that the proposed algorithms can effectively minimize the expected energy consumption.},
}

@inproceedings { DBLP:conf/rtas/ChenYLK08,
  author = {Chen, Jian-Jia and Yang, Chuan-Yue and Lu, Hsueh-I and Kuo, Tei-Wei},
  title = {Approximation Algorithms for Multiprocessor Energy-Efficient Scheduling of Periodic Real-Time Tasks with Uncertain Task Execution Time},
  booktitle = {Proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2008, April 22-24, 2008, St. Louis, Missouri, USA},
  date-modified = {2015-08-27 13:26:12 +0000},
  year = {2008},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2008.24},
  pages = {13-23},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2008.24},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-efficiency has been an important system issue in hardware and software designs for both real-time embedded systems and server systems.??This research explores systems with probabilistic distribution on the execution time of real-time tasks on homogeneous multiprocessor platforms with the capability of dynamic voltage scaling (DVS). The objective is to derive a task partition which minimizes the expected energy consumption for completing all the given tasks in time.??We give an efficient 1.13-approximation algorithm and a polynomial-time approximation scheme (PTAS) to provide worst-case guarantees for the strongly NP-hard problem. Experimental results show that the algorithms can effectively minimize the expected energy consumption.},
}

@inproceedings { DBLP:conf/rtss/ZhuAC08,
  author = {Zhu, Dakai and Aydin, Hakan and Chen, Jian-Jia},
  title = {Optimistic Reliability Aware Energy Management for Real-Time Tasks with Probabilistic Execution Times},
  booktitle = {Proceedings of the 29th IEEE Real-Time Systems Symposium, RTSS 2008, Barcelona, Spain, 30 November - 3 December 2008},
  date-modified = {2015-08-27 13:26:30 +0000},
  year = {2008},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2008.37},
  pages = {313-322},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2008.37},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Reliability-aware power management (RAPM) schemes have been recently studied to save energy while preserving system reliability. The existing RAPM schemes, however, provision for worst-case execution scenarios and are rather conservative. In this paper, by exploiting the probabilistic execution time information of real-time tasks, we develop an optimistic RAPM scheme. Instead of scheduling a full recovery for tasks whose executions are scaled down, the new scheme puts aside just enough slack to guarantee the required reliability leave while leaving more slack for energy management to achieve better energy savings. The problem is shown to be NP-hard and a novel heuristic algorithm is proposed and evaluated. The simulation results show that the optimistic RAPM scheme performs very well. It achieves energy savings comparable to that of the ordinary (but reliability-ignorant) power management scheme, while maintaining the system reliability as successfully as the conservative RAPM schemes.},
}

@inproceedings { DBLP:conf/icpads/ChenT08,
  author = {Chen, Jian-Jia and Thiele, Lothar},
  title = {Energy-Efficient Task Partition for Periodic Real-Time Tasks on Platforms with Dual Processing Elements},
  booktitle = {14th International Conference on Parallel and Distributed Systems (ICPADS 2008), December 8-10, 2008, Melbourne, Victoria, Australia},
  date-modified = {2015-08-27 13:26:21 +0000},
  year = {2008},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ICPADS.2008.123},
  pages = {161-168},
  url = {http://dx.doi.org/10.1109/ICPADS.2008.123},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Modern computing systems often adopt multiple processing elements to enhance the computing capability or reduce the power consumption, especially for embedded systems. Such configurations impose challenges on energy efficiency in hardware and software implementations. This paper targets energy-efficient task partitioning for real-time tasks on a platform with two heterogeneous processing elements (processors), in which each one has its own characteristics on power consumption and job execution. This paper proposes a general framework for different hardware configurations in energy/power consumption. The framework provides a fully polynomial-time approximation scheme (FPTAS) to derive a solution with energy consumption very close to the optimal energy consumption in tolerable time/space complexity. Experimental results reveal that the proposed framework is effective in energy efficiency.},
}

@inproceedings { DBLP:conf/rtcsa/MoserCT08,
  author = {Moser, Clemens and Chen, Jian-Jia and Thiele, Lothar},
  title = {Reward Maximization for Embedded Systems with Renewable Energies},
  booktitle = {The Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2008, Kaohisung, Taiwan, 25-27 August 2008, Proceeding},
  date-modified = {2015-08-27 13:26:33 +0000},
  year = {2008},
  bdsk-url-1 = {http://dx.doi.org/10.1109/RTCSA.2008.25},
  pages = {247-256},
  url = {http://dx.doi.org/10.1109/RTCSA.2008.25},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Renewable energies can enable embedded systems to be functional indefinitely. In particular for small autonomous sensors, energy harvesting techniques have attracted much interest. This paper considers systems which provide services periodically with adjustable quality evaluated in terms of rewards. The reward garnered for one service is monotonically increasing and strictly concave with respect to the energy consumption of the service. There exist two major constraints which arise due to the burstiness of common energy sources: (1) The harvested energy is temporarily low and the service must be lowered or suspended. (2) During bursts, the harvested energy exceeds the battery capacity. To resolve these issues, we propose algorithms to derive optimal solutions which maximize the overall reward. Furthermore, we determine the minimum battery capacity necessary to optimally exploit a given power source. By applying real data recorded for photovoltaic cells as the harvested energy, simulations illuminate the merits of our algorithms.},
}

@inproceedings { DBLP:conf/date/ChenKYK07,
  author = {Chen, Jian-Jia and Kuo, Tei-Wei and Yang, Chia-Lin and King, Ku-Jei},
  title = {Energy-efficient real-time task scheduling with task rejection},
  booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition (DATE 2007), April 16-20, 2007, Nice, France},
  date-modified = {2015-08-27 13:23:59 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1266366.1266724},
  pages = {1629-1634},
  url = {http://doi.acm.org/10.1145/1266366.1266724},
  keywords = {jj-old},
  confidential = {n},
  abstract = {In the past decade, energy-efficiency has been an important system design issue in both hardware and software managements. For mobile applications with critical missions, both energy consumption reduction and timing guarantee have to be provided by system engineers to extend operation duration and maintain system stability. This research explores real-time systems composed of homogeneous multiple processors with the capability of dynamic voltage scaling (DVS), in which a given task can be rejected with a specified value of rejection penalty. The objective is to minimize the summation of the total rejection penalty for the tasks that are not completed in time and the energy consumption of the system. This study provides analysis to show that there does not exist any polynomial-time approximation algorithm for the studied problem, unless P = NP. Moreover, we propose algorithms for systems with ideal and non-ideal DVS processors. The capability of the proposed algorithms is provided with extensive evaluations. The evaluation results reveal that our proposed algorithms could derive effective solutions of the energy-efficient scheduling problem with task rejection considerations.},
}

@inproceedings { DBLP:conf/cases/ChiYCC07,
  author = {Chi, Jaw-Wei and Yang, Chia-Lin and Chen, Yi-Jung and Chen, Jian-Jia},
  title = {Cache leakage control mechanism for hard real-time systems},
  booktitle = {Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007},
  date-modified = {2015-08-27 13:23:46 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1289881.1289924},
  pages = {248-256},
  url = {http://doi.acm.org/10.1145/1289881.1289924},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor's transistor budget, several leakage control policies have been proposed to reduce cache leakage. However, these policies introduce performance unpredictability thereby not suitable for hard real-time applications that require the timing constraint is met in all cases. In this paper, we propose the first approach to apply existing low leakage circuit techniques on hard real-time applications. The proposed timing-aware cache leakage control mechanism exploits task slack time to turn cache lines into the low-leakage state provided that the timing constraint is met. The experimental results show that the proposed cache leakage control policy achieves comparable leakage reduction to the leakage control policy that aggressively turn cache lines into low-leakage modes without considering the timing constraint.},
}

@inproceedings { DBLP:conf/iccad/ChenK07,
  author = {Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems},
  booktitle = {2007 International Conference on Computer-Aided Design (ICCAD'07), November 5-8, 2007, San Jose, CA, USA},
  date-modified = {2015-08-27 13:24:17 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1326073.1326132},
  pages = {289-294},
  url = {http://doi.acm.org/10.1145/1326073.1326132},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Many computing systems have adopted the dynamic voltage scaling (DVS) technique to reduce energy consumption by slowing down operation speed. However, the longer a job executes, the more energy in leakage current the processor consumes for the job. To reduce the power/energy consumption from the leakage current, a processor can enter the dormant mode. Existing research results for leakage-aware DVS scheduling perform procrastination of real-time jobs greedily so that the idle time can be aggregated as long as possible to turn off the processor. This paper proposes algorithms for the procrastination determination of periodic real-time tasks in uniprocessor systems. Instead of greedy procrastination, the procrastination procedures are applied only when the evaluated energy consumption is less than not procrastination. Evaluation results show that our proposed algorithms could derive energy-efficient solutions and outperform existing algorithms.},
}

@inproceedings { DBLP:conf/aspdac/ChenYKS07,
  author = {Chen, Jian-Jia and Yang, Chuan-Yue and Kuo, Tei-Wei and Shih, Chi-Sheng},
  title = {Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems},
  booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007},
  date-modified = {2015-08-27 13:23:56 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358009},
  pages = {342-349},
  url = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358009},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Dynamic voltage scaling (DVS) circuits have been widely adopted in many computing systems to provide tradeoff between performance and power consumption. The effective use of energy could not only extend operation duration for hand-held devices but also cut down power bills of server systems. Moreover, while many chip makers are releasing multi-core chips and multiprocessor system-on-a-chips (SoCs), multiprocessor platforms for different applications become even more popular. Multiprocessor platforms could improve the system performance and accommodate the growing demand of computing power and the variety of application functionality. This paper summarizes our work on several important issues in energy-efficient scheduling for real-time tasks in multiprocessorDVS systems. Distinct from most previous work based on heuristics, we aim at the provision of approximated solutions with worst-case guarantees. The proposed algorithms are evaluated by a series of experiments to provide insights in system designs.},
}

@inproceedings { DBLP:conf/aspdac/ChenIKL07,
  author = {Chen, Jian-Jia and Iwama, Kazuo and Kuo, Tei-Wei and Lu, Hsueh-I},
  title = {Flow Time Minimization under Energy Constraints},
  booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007},
  date-modified = {2015-08-27 13:24:06 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358098},
  pages = {866-871},
  url = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358098},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Power-aware and energy-efficient designs play important roles for modern hardware and software designs, especially for embedded systems. This paper targets a scheduling problem on a processor with the capability of dynamic voltage scaling (DVS), which could reduce the power consumption by slowing down the processor speed. The objective of the targeting problem is to minimize the average flow time of a set of jobs under a given energy constraint, where the flow time of a job is defined as the interval length between the arrival and the completion of the job. We consider two types of processors, which have a continuous spectrum of the available speeds or have only a finite number of discrete speeds. Two algorithms are given: (1) An algorithm is proposed to derive optimal solutions for processors with a continuous spectrum of the available speeds. (2) A greedy algorithm is designed for the derivation of optimal solutions for processors with a finite number of discrete speeds. The proposed algorithms are extended to cope with jobs with different weights for the minimization of the average weighted flow time. The proposed algorithms are also evaluated with comparisons to schedules which execute jobs at a common effective speed.},
}

@inproceedings { DBLP:conf/isorc/YangCHK07,
  author = {Yang, Chuan-Yue and Chen, Jian-Jia and Hung, Chia-Mei and Kuo, Tei-Wei},
  title = {System-Level Energy-Efficiency for Real-Time Tasks},
  booktitle = {Tenth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2007), 7-9 May 2007, Santorini Island, Greece},
  date-modified = {2015-08-27 13:24:24 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/ISORC.2007.55},
  pages = {266-273},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISORC.2007.55},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Dynamic voltage scaling (DVS) has been adopted in many computing systems to reduce the energy consumption of the processor by slowing down the processor speed. However, for system devices without DVS capability, the longer a task executes, the more energy the task consumes in the required system devices. This paper explores energy-efficient scheduling for periodic hard real-time tasks in a system consisted of a DVS processor and multiple non- DVS system devices. We propose an algorithm for static scheduling which minimizes the system energy consumption of a given set of real-time tasks, provided that each task executes in its worst case. For systems in which some tasks might complete earlier than its estimated worst-case execution time, we develop on-line algorithms to reclaim the slack time to reduce the energy consumption. Compared to existing algorithms, our proposed algorithm can reduce the energy consumption both in the CPU and system devices.},
}

@inproceedings { DBLP:conf/rtas/ChenHK07,
  author = {Chen, Jian-Jia and Hung, Chia-Mei and Kuo, Tei-Wei},
  title = {On the Minimization fo the Instantaneous Temperature for Periodic Real-Time Tasks},
  booktitle = {Proceedings of the 13th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2007, April 3-6, 2007, Bellevue, Washington, USA},
  date-modified = {2015-08-27 13:24:10 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2007.21},
  pages = {236-248},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2007.21},
  keywords = {jj-old},
  confidential = {n},
  abstract = {While there is a tradeoff between the energy consumption and the satisfaction of task deadlines, the management of the processor temperature is of paramount important to the survival of the processor and the reduction of packing cost. This paper explores the scheduling of periodic real-time tasks with temperature-aware considerations in a uniprocessor or homogeneous multi-processor environment. By modeling the cooling process approximately according to Fourier?s Law, a 2.719-approximation algorithm is shown for the minimization of the maximum temperature for processors with continuous processor speeds. When the processor is with discrete speeds only, we extend the 2.719-approximation algorithm to manage the voltage/speed transition so that the maximum temperature can be minimized. For homogeneous multiprocessor systems, we show that the largest-taskfirst strategy has a 3.072-approximation bound in the minimization of the maximum temperature when all of the processors are on a chip. When each processor is on a chip, the approximation bound in the minimization of the maximum temperature is 6.444. When jobs might complete earlier than their worst-case estimation, dynamic scheduling is further explored to reduce the maximum temperature.},
}

@inproceedings { DBLP:conf/rtas/ChenYKT07,
  author = {Chen, Jian-Jia and Yang, Chuan-Yue and Kuo, Tei-Wei and Tseng, Shau-Yin},
  title = {Real-Time Task Replication for Fault Tolerance in Identical Multiprocessor Systems},
  booktitle = {Proceedings of the 13th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2007, April 3-6, 2007, Bellevue, Washington, USA},
  date-modified = {2015-08-27 13:24:20 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2007.30},
  pages = {249-258},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2007.30},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Multiprocessor platforms have been widely adopted in both embedded and server systems. In addition to the performance improvement, multiprocessor systems could have the flexibility in tolerating processor failures via task replication. This paper considers the replication of periodic hard real-time tasks in identical multiprocessor environments. Each task is replicated on K distinct processors, where K is a user-determined integer for fault tolerance to improve system reliability. When the objective is to minimize the maximum utilization in a system with a specified number of processors, we present a greedy algorithm with a 2-approximation ratio, and a polynomial-time approximation scheme is developed. For the minimization of the number of processors required to derive feasible schedules with task replication, we develop greedy algorithms with a 2- approximation ratio and an asymptotic polynomial-time approximation scheme.},
}

@inproceedings { DBLP:conf/rtcsa/ChenK07,
  author = {Chen, Jian-Jia and Kuo, Chin-Fu},
  title = {Energy-Efficient Scheduling for Real-Time Systems on Dynamic Voltage Scaling (DVS) Platforms},
  booktitle = {13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea},
  date-modified = {2015-08-27 13:24:02 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2007.37},
  pages = {28-38},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2007.37},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-efficient designs have played import roles for hardware and software implementations for a decade. With the advanced technology of VLSI circuit designs, energy-efficiency can be achieved by adopting the dynamic voltage scaling (DVS) technique. In this paper, we survey the studies for energy-efficient scheduling in real-time systems on DVS platforms to cover both theoretical and practical issues.},
}

@inproceedings { DBLP:conf/rtcsa/YangCK07,
  author = {Yang, Chuan-Yue and Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Preemption Control for Energy-Efficient Task Scheduling in Systems with a DVS Processor and Non-DVS Devices},
  booktitle = {13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 21-24 August 2007, Daegu, Korea},
  date-modified = {2015-08-27 13:24:13 +0000},
  year = {2007},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2007.56},
  pages = {293-300},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2007.56},
  keywords = {jj-old},
  confidential = {n},
  abstract = {In reality, peripheral devices often make a significant contribution to the power consumption of the entire system. An effective energy-efficient scheduling algorithm should consider not only the energy consumption of the processor but also the usages of devices. In this paper, we explore energyefficient scheduling of periodic real-time tasks in a system with a dynamic-voltage-scaling (DVS) processor and multiple non- DVS system devices. We consider systems that any device used by a task remains operating while the task is active. We propose scheduling algorithms in the management of task preemption to reduce the energy consumption of devices. Simulation results show that our proposed algorithms could not only reduce the number of task preemption significantly but also minimize the energy consumption, compared to earliest-deadlinefirst scheduling.},
}

@inproceedings { DBLP:conf/euc/LeeCK07,
  author = {Lee, Yung-Hen and Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Energy-Efficiency on a Variable-Bitrate Device},
  booktitle = {Emerging Directions in Embedded and Ubiquitous Computing, EUC 2007 Workshops: TRUST, WSOC, NCUS, UUWSN, USN, ESO, and SECUBIQ, Taipei, Taiwan, December 17-20, 2007, Proceedings},
  date-modified = {2015-08-27 13:23:51 +0000},
  year = {2007},
  bdsk-url-1 = {http://dx.doi.org/10.1007/978-3-540-77090-9_56},
  pages = {604-616},
  url = {http://dx.doi.org/10.1007/978-3-540-77090-9_56},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Dynamic power management has been adopted in many systems to reduce the power/energy consumption by changing the system state dynamically. This paper explores energy efficiency for systems equipped with PCI-Express devices, which are designed for low power consumption and high performance, compared to corresponding PCI devices. We propose dynamic power management mechanism and a management policy for energy-efficient considerations. A case study for a variable-bit-rate local-area-network device under the PCI-Express specification is exploited to provide supports for dynamic packet transmission. Simulation results show that the proposed mechanism and policy would reduce the system energy consumption substantially.},
}

@inproceedings { DBLP:conf/date/HsuCK06,
  author = {Hsu, Heng-Ruey and Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint},
  booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006},
  date-modified = {2015-08-27 13:23:37 +0000},
  year = {2006},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1131776},
  pages = {1061-1066},
  url = {http://doi.acm.org/10.1145/1131776},
  keywords = {jj-old},
  confidential = {n},
  abstract = {The energy-aware design for electronic systems has been an important issue in hardware and/or software implementations, especially for embedded systems. This paper targets a synthesis problem for heterogeneous multiprocessor systems to schedule a set of periodic real-time tasks under a given energy consumption constraint. Each task is required to execute on a processor without migration, where tasks might have different execution times on different processor types. Our objective is to minimize the processor cost of the entire system under the given timing and energy consumption constraints. The problem is first shown being NP-hard and having no polynomial-time algorithm with a constant approximation ratio unless NP = P. We propose polynomial-time approximation algorithms with (m + 2)-approximation ratios for this challenging problem, where m is the number of the available processor types. Experimental results show that the proposed algorithms could always derive solutions with system costs close to those of optimal solutions.},
}

@inproceedings { DBLP:conf/lctrts/ChenK06,
  author = {Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor},
  booktitle = {Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Ontario, Canada, June 14-16, 2006},
  date-modified = {2015-08-27 13:23:40 +0000},
  year = {2006},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1134650.1134673},
  pages = {153-162},
  url = {http://doi.acm.org/10.1145/1134650.1134673},
  keywords = {jj-old},
  confidential = {n},
  abstract = {As the dynamic voltage scaling (DVS) technique provides system engineers the flexibility to trade-off the performance and the energy consumption, DVS has been adopted in many computing systems. However, the longer a job executes, the more energy in the leakage current the device/processor consumes for the job. To reduce the energy consumption resulting from the leakage current, a system might enter the dormant mode. This paper targets energy-efficient rate-monotonic scheduling for periodic real-time tasks on a uniprocessor DVS system with non-negligible leakage power consumption. An on-line simulated scheduling strategy and a virtually blocking time strategy are developed for procrastination scheduling to reduce energy consumption. The proposed algorithms derive a feasible schedule for real-time tasks with worst-case guarantees for any input instance. Experimental results show that our proposed algorithms could derive energy-efficient solutions.},
}

@inproceedings { DBLP:conf/iccad/ChenK06,
  author = {Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systems},
  booktitle = {2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA},
  date-modified = {2015-08-27 13:23:02 +0000},
  year = {2006},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1233501.1233552},
  pages = {255-260},
  url = {http://doi.acm.org/10.1145/1233501.1233552},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-efficiency and power-awareness for electronic systems have been important design issues in hardware and software implementations. We consider the scheduling of periodic hard real-time tasks along with the allocation of processors under a given energy constraint. Each processor type could be associated with its allocation cost. The objective of this work is to minimize the entire allocation cost of processors so that the timing and energy constraints are both satisfied. We develop approximation algorithms for processor types with continuous processor speeds or discrete processor speeds. The capability of the proposed algorithms was evaluated by a series of experiments, and it was shown that the proposed algorithms always derived solutions with system costs close to those of optimal solutions in the experiments.},
}

@inproceedings { DBLP:conf/rtas/ChenHK06,
  author = {Chen, Jian-Jia and Hsu, Heng-Ruey and Kuo, Tei-Wei},
  title = {Leakage-Aware Energy-Efficient Scheduling of Real-Time Tasks in Multiprocessor Systems},
  booktitle = {12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), 4-7 April 2006, San Jose, California, USA},
  date-modified = {2015-08-27 13:23:34 +0000},
  year = {2006},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2006.25},
  pages = {408-417},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTAS.2006.25},
  keywords = {jj-old},
  confidential = {n},
  abstract = {This work targets energy-efficient scheduling of periodic real-time tasks over multiple DVS processors with the considerations of power consumption due to leakage current. A polynomial-time algorithm with a 1.283 approximation bound is proposed when the overheads in turning on/off a processor are negligible. When the overheads are non-negligible, we develop polynomial-time algorithms with a 2 approximation bound. A series of simulation experiments was done for the performance evaluation of the proposed algorithms. The simulation results show that the proposed algorithms could derive schedules very close to optimal solutions.},
}

@inproceedings { DBLP:conf/rtss/HungCK06,
  author = {Hung, Chia-Mei and Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Energy-Efficient Real-Time Task Scheduling for a DVS System with a Non-DVS Processing Element},
  booktitle = {Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), 5-8 December 2006, Rio de Janeiro, Brazil},
  date-modified = {2015-08-27 13:23:16 +0000},
  year = {2006},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2006.22},
  pages = {303-312},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2006.22},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Multiple processing elements are often adopted in the current designs of embedded systems. Such configurations impose challenges on hardware/software co-designs with energy-efficient considerations. This paper targets energy-efficient real-time task scheduling of such popular configurations, in which systems are equipped with a DVS processor and a non-DVS processing element (PE). We consider task scheduling under different power consumption models of the non-DVS PE. When the power consumption of the non-DVS PE is independent on the assigned workload, a fully polynomial-time approximation scheme is developed for energy-efficient scheduling. When the energy consumption of the non-DVS PE depends on the assigned workload, a 0.5-approximation algorithm is developed to maximize the energy saving, compared to the execution of tasks on a DVS processor. Extensive simulations were performed to evaluate the capability of our proposed algorithms. The results show that our algorithms are very effective in energy-efficiency.},
}

@inproceedings { DBLP:conf/sutc/ChenYK06,
  author = {Chen, Jian-Jia and Yang, Chuan-Yue and Kuo, Tei-Wei},
  title = {Slack Reclamation for Real-Time Task Scheduling over Dynamic Voltage Scaling Multiprocessors},
  booktitle = {IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC 2006), 5-7 June 2006, Taichung, Taiwan},
  date-modified = {2015-08-27 13:23:44 +0000},
  year = {2006},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/SUTC.2006.126},
  pages = {358-367},
  url = {http://doi.ieeecomputersociety.org/10.1109/SUTC.2006.126},
  keywords = {jj-old},
  confidential = {n},
  abstract = {In the past decades, a number of research results have been reported for energy-efficient task scheduling over uniprocessor and multiprocessor environments. While researchers have started the exploring of slack reclaiming for tasks during run time, little work has been done for multiprocessor cases. This paper proposes a set of multiprocessor energy-efficient task scheduling algorithms with different task remapping and slack reclaiming schemes, where tasks have the same arrival time and share a common deadline. Tasks are reassigned to processors dynamically, and the slack time is reclaimed to slow down the execution speeds of the remaining tasks for energy efficiency. Extensive simulations were performed to provide insights. The energy consumption could be reduced up to 29% in the experiments, compared to the previous work.},
}

@inproceedings { DBLP:conf/iscas/PerngCYK06,
  author = {Perng, Nei-Chiung and Chen, Jian-Jia and Yang, Chuan-Yue and Kuo, Tei-Wei},
  title = {Energy-efficient scheduling on multi-context FPGAs},
  booktitle = {International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece},
  date-modified = {2015-08-27 13:23:25 +0000},
  year = {2006},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ISCAS.2006.1692830},
  url = {http://dx.doi.org/10.1109/ISCAS.2006.1692830},
  keywords = {jj-old},
  confidential = {n},
  abstract = {This work is motivated by the needs of energy-efficient designs for multi-context FPGAs. Dynamic-voltage-scaling-based algorithms are proposed to schedule loading and executing of tasks in a multi-context FPGA. When a task partition over contexts is given, two optimal scheduling algorithms are proposed in minimizing the energy consumption and the maximum time span of task executions. When no task partition is given, two approximation algorithms with approximation ratios 2.371 and 1.540 are presented in the energy-consumption minimization and the maximum-time-span minimization, respectively},
}

@inproceedings { DBLP:conf/pdcs/WuCHK05,
  author = {Wu, Jun and Chen, Jian-Jia and Hsueh, Chih-wen and Kuo, Tei-Wei},
  title = {Scheduling of Query Execution Plans in Distributed-Memory Multiprocessor Database Systems},
  booktitle = {International Conference on Parallel and Distributed Computing Systems, PDCS 2005, November 14-16, 2005, Phoenix, AZ, USA},
  date-modified = {2015-08-27 13:21:34 +0000},
  year = {2005},
  pages = {113-118},
  keywords = {jj-old},
  confidential = {n},
  abstract = {For multiprocessor database systems, the scheduling of query execution plans (QEPs) is to map the physical op erators onto processors and execute them without violating their partial order. In this paper, we propose an algorithm for optimizing the schedule length for a collection of QEPs in a distributed-memory multiprocessor (DMM) database system, called physical operator scheduling (POS) algo rithm. We show that the worst schedule length of the POS algorithm is no more than 3 times the optimal sched ule length. The performance of our proposed algorithms were evaluated for input instances generated based on the TPC benchmark [1] and on a pseudo-random number gen erator. The experimental results show that our proposed scheduling algorithms is significantly outperform previous approaches.},
}

@inproceedings { DBLP:conf/emsoft/ChenKS05,
  author = {Chen, Jian-Jia and Kuo, Tei-Wei and Shih, Chi-Sheng},
  title = {(1+epsion) approximation clock rate assignment for periodic real-time tasks on a voltage-scaling processor},
  booktitle = {EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings},
  date-modified = {2015-08-27 13:20:13 +0000},
  year = {2005},
  bdsk-url-1 = {http://doi.acm.org/10.1145/1086228.1086273},
  pages = {247-250},
  url = {http://doi.acm.org/10.1145/1086228.1086273},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-efficient scheduling is an effective way to balance the system performance and the energy consumption. We design a polynomial-time (1+ε)-approximation algorithm to minimize the energy consumption for periodic real-time tasks over such processors, where ε is the tolerable error given by users (1 ≥ ε > 0). It provides trade-offs between the user's tolerable error and the runtime complexity including the time complexity and the memory space complexity. System engineers could trade performance with implementation constraints.},
}

@inproceedings { DBLP:conf/date/YangCK05,
  author = {Yang, Chuan-Yue and Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor},
  booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany},
  date-modified = {2015-08-27 13:21:05 +0000},
  year = {2005},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.51},
  pages = {468-473},
  url = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.51},
  keywords = {jj-old},
  confidential = {n},
  abstract = {In the recent decade, voltage scaling has become an attractive feature for many system component designs. In this paper, we consider energy-efficient real-time task scheduling over a chip multiprocessor architecture. The objective is to schedule a set of frame-based tasks with the minimum energy consumption, where all tasks are ready at time 0 and share a common deadline. We show that such a minimization problem is NP-hard and then propose a 2.371-approximation algorithm. The strength of the proposed algorithm was demonstrated by a series of simulations, for which near optimal results were obtained.},
}

@inproceedings { DBLP:conf/rtcsa/ChenWSK05,
  author = {Chen, Jian-Jia and Wu, Jun and Shih, Chi-Sheng and Kuo, Tei-Wei},
  title = {Approximation Algorithms for Scheduling Multiple Feasible Interval Jobs},
  booktitle = {11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 17-19 August 2005, Hong Kong, China},
  date-modified = {2015-08-27 13:21:10 +0000},
  year = {2005},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2005.28},
  pages = {11-16},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTCSA.2005.28},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Time-critical jobs in many real-time applications have multiple feasible intervals. Such a job is constrained to execute from start to completion in one of its feasible intervals. A job fails if the job remains incomplete at the end of the last feasible interval. This paper is concerned with how to find a schedule in which the number of jobs completed in one of their feasible intervals is maximized. We show that the maximization problem is NP-hard for both non-preemptible and preemptible jobs. This paper develops two approximation algorithms for non-preemptible and preemptible jobs. When jobs are non-preemptible, Algorithm LECF is with a 2-approximation factor; when jobs are preemptible, Algorithm LEF is proved being a 3-approximation algorithm. We also show that our analysis on the two algorithms is tight by providing a set of input instances. Simulation results demonstrate that Algorithms LECF and LEF not only guarantee the approximation factors but also outperform other multiple feasible interval scheduling algorithms.},
}

@inproceedings { DBLP:conf/rtss/ChenK05,
  author = {Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Voltage Scaling Scheduling for Periodic Real-Time Tasks in Reward Maximization},
  booktitle = {Proceedings of the 26th IEEE Real-Time Systems Symposium (RTSS 2005), 6-8 December 2005, Miami, FL, USA},
  date-modified = {2015-08-27 13:21:39 +0000},
  year = {2005},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2005.44},
  pages = {345-355},
  url = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2005.44},
  keywords = {jj-old},
  confidential = {n},
  abstract = {This paper is interested in reward maximization of periodic real-time tasks under a given energy constraint, where the reward received depends on how much computation a task runs before its deadline. When voltage scaling could be done at any time, and tasks share the same power consumption function, we propose a greedy algorithm which derives a solution with at least a half of the optimal reward for any input instance. A fully polynomial-time approximation scheme is also proposed by applying the dynamic programming approach so that the ratio of the reward of the derived solution to that of an optimal solution is at least $1-\epsilon$ under polynomial-time complexity in $1/\epsilon$ for any $0 < \epsilon < 1$, where $\epsilon$ denotes a user-specified tolerable error to the derived solutions. When voltage scaling could be done only when a task instance arrives or terminates, or tasks might have different power consumption functions, we develop an approximation algorithm based on linear programming, which guarantees to derive a solution with at least 1/3 optimal reward for any input instance. A series of experiments was conducted to show the capability of the proposed algorithms in reward maximization.},
}

@inproceedings { DBLP:conf/wads/ChenKL05,
  author = {Chen, Jian-Jia and Kuo, Tei-Wei and Lu, Hsueh-I},
  title = {Power-Saving Scheduling for Weakly Dynamic Voltage Scaling Devices},
  booktitle = {Algorithms and Data Structures, 9th International Workshop, WADS 2005, Waterloo, Canada, August 15-17, 2005, Proceedings},
  date-modified = {2015-08-27 13:21:30 +0000},
  year = {2005},
  bdsk-url-1 = {http://dx.doi.org/10.1007/11534273_30},
  pages = {338-349},
  url = {http://dx.doi.org/10.1007/11534273_30},
  keywords = {jj-old},
  confidential = {n},
  abstract = {We study the problem of non-preemptive scheduling to minimize energy consumption for devices that allow dynamic voltage scaling. Specifically, consider a device that can process jobs in a non-preemptive manner. The input consists of (i) the set $R$ of available speeds of the device, (ii) a set $J$ of jobs, and (iii) a precedence constraint \Pi among $J$. Each job $j$ in $J$, defined by its arrival time $a_j$ , deadline $d_j$ , and amount of computation $c_j$ , is supposed to be processed by the device at a speed in $R$. Under the assumption that a higher speed means higher energy consumption, the power-saving scheduling problem is to compute a feasible schedule with speed assignment for the jobs in J such that the required energy consumption is minimized. This paper focuses on the setting of weakly dynamic voltage scaling, i.e., speed change is not allowed in the middle of processing a job. To demonstrate that this restriction on many portable power-aware devices introduces hardness to the power-saving scheduling problem, we prove that the problem is NP-hard even if $a_j = a_j'$ and $d_j = d_j'$ hold for all $j,j'\in J$ and $|R|=2$. If $|R|<\infty$, we also give fully polynomial-time approximation schemes for two cases of the general NP-hard problem: (a) all jobs share a common arrival time, and (b) $\Pi = \varnothing$ and for any $j,j' \in J, a_j \leq a_j'$ implies $d_j \leq d_j'$. To the best of our knowledge, there is no previously known approximation algorithm for any special case of the NP-hard problem.},
}

@inproceedings { DBLP:conf/globecom/ChenLKYP05,
  author = {Chen, Jian-Jia and Lu, Hsueh-I and Kuo, Tei-Wei and Yang, Chuan-Yue and Pang, Ai-Chun},
  title = {Dual power assignment for network connectivity in wireless sensor networks},
  booktitle = {Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November - 2 December 2005},
  date-modified = {2015-08-27 13:21:21 +0000},
  year = {2005},
  bdsk-url-1 = {http://dx.doi.org/10.1109/GLOCOM.2005.1578450},
  pages = {5},
  url = {http://dx.doi.org/10.1109/GLOCOM.2005.1578450},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Strong connectivity has been an important feature explored in many network applications, such as sensor networks. This research focuses on a dual power assignment problem, where each sensor node has two transmission power levels. The objective is to minimize the number of wireless sensor nodes assigned to transmit messages at the high transmission power level, while the resulting sensor network is strongly connected. We propose an efficient 1.75-approximation algorithm for this challenging problem. We not only show that the approximation ratio of the proposed algorithm is tight but also demonstrate the capability of the proposed algorithm in terms of simulation experiments},
}

@inproceedings { DBLP:conf/icpp/ChenK05,
  author = {Chen, Jian-Jia and Kuo, Tei-Wei},
  title = {Multiprocessor Energy-Efficient Scheduling for Real-Time Tasks with Different Power Characteristics},
  booktitle = {34th International Conference on Parallel Processing (ICPP 2005), 14-17 June 2005, Oslo, Norway},
  date-modified = {2015-08-27 13:21:26 +0000},
  year = {2005},
  bdsk-url-1 = {http://dx.doi.org/10.1109/ICPP.2005.53},
  pages = {13-20},
  url = {http://dx.doi.org/10.1109/ICPP.2005.53},
  keywords = {jj-old},
  confidential = {n},
  abstract = {In the past decades, a number of research results have been reported for energy-efficient scheduling over uniprocessor and multiprocessor environments. Different from many of the past results on the assumption for task power characteristics, we consider real-time scheduling of tasks with different power characteristics. The objective is to minimize the energy consumption of task executions under the given deadline constraint. When tasks have a common deadline and are ready at time 0, we propose an optimal real-time task scheduling algorithm for multiprocessor environments with the allowance of task migration. When no task migration is allowed, a 1.412-approximation algorithm for task scheduling is proposed for different settings of power characteristics. The performance of the approximation algorithm was evaluated by an extensive set of experiments, where excellent results were reported.},
}

@inproceedings { DBLP:conf/iiwas/TsaiCKS04,
  author = {Tsai, Yi-Hua and Chen, Jian-Jia and Kuo, Tei-Wei and Shih, Chi-Sheng},
  title = {Client and Server Mobility for WEB Applications},
  booktitle = {iiWAS'2004 - The sixth International Conference on Information Integrationand Web-based Applications Services, 27-29 September 2004, Jakarta, Indonesia},
  date-modified = {2015-08-27 13:20:23 +0000},
  year = {2004},
  keywords = {jj-old},
  confidential = {n},
  abstract = {As mobile devices and broadband networks are widely available, it is desirable to provide mobility for web services. A web service is mobile in the sense that, without interrupting the services, users are allowed to switch the browsing devices or the service providing servers could be changed as the users move. The mobility of users' browsing devices and the change of service providing servers are called client mobility and server mobility, respectively. This paper develops an innovative approach, which does not require any third-party agents, for realizing client mobility and server mobility. Hence, the approach introduces less overhead and provides better backward compatibility for existing services. Only a plug-in module for the web browsing devices is needed to provide the client and server mobility services. The approach has been demonstrated using one of the popular web clients, Konqueror, and one of the popular web servers, Apache.},
}

@inproceedings { DBLP:conf/sac/ChenKY04,
  author = {Chen, Jian-Jia and Kuo, Tei-Wei and Yang, Chia-Lin},
  title = {Profit-driven uniprocessor scheduling with energy and timing constraints},
  booktitle = {Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), Nicosia, Cyprus, March 14-17, 2004},
  date-modified = {2015-08-27 13:20:45 +0000},
  year = {2004},
  bdsk-url-1 = {http://doi.acm.org/10.1145/967900.968072},
  pages = {834-840},
  url = {http://doi.acm.org/10.1145/967900.968072},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-aware scheduling has received much attention in recent years, especially for systems with serious considerations on energy consumption. While most previous work focuses on the minimization of energy consumption, this paper exploits the maximization of the entire system profit under energy and timing constraints. We propose a greedy approximation algorithm with a 2-approximation ratio. A fully polynomial time approximation scheme (FPTAS) is also proposed, which is an optimal approximation algorithm unless P = NP. For each specified amount of error tolerant to users, the approximation algorithm could provide trade-offs among the specified error, the running time, the approximation ratio, and the memory space complexity. It provides ways for system engineers to trade performance with implementation constraints.},
}

@inproceedings { DBLP:conf/ecrts/ChenHCYPK04,
  author = {Chen, Jian-Jia and Hsu, Heng-Ruey and Chuang, Kai-Hsiang and Yang, Chia-Lin and Pang, Ai-Chun and Kuo, Tei-Wei},
  title = {Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations},
  booktitle = {16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June - 2 July 1004, Catania, Italy, Proceedings},
  date-modified = {2015-08-27 13:20:35 +0000},
  year = {2004},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/ECRTS.2004.20},
  pages = {101-108},
  url = {http://doi.ieeecomputersociety.org/10.1109/ECRTS.2004.20},
  keywords = {jj-old},
  confidential = {n},
  abstract = {This paper targets energy-efficient scheduling of tasks over multiple processors, where tasks share a common deadline. Distinct from many research results on heuristics-based energy-efficient scheduling, we propose approximation algorithms with different approximation bounds for processors with/without constraints on the maximum processor speed, where no task migration is allowed. When there is no constraint on processor speeds, we propose an approximation algorithm for two-processor scheduling to provide trade-offs among the specified error, the running time, the approximation ratio, and the memory space complexity. An approximation algorithm with a 1.13-approximation ratio for M-processor systems is also derived (M > 2). When there is an upper bound on processor speeds, an artificial-bound approach is taken to minimize the energy consumption with a 1.13-approximation ratio. An optimal scheduling algorithm is then proposed in the minimization of the energy consumption when task migration is allowed.},
}

@inproceedings { DBLP:conf/ipps/WuCHK04,
  author = {Wu, Jun and Chen, Jian-Jia and Hsueh, Chih-wen and Kuo, Tei-Wei},
  title = {Scheduling of Query Execution Plans in Symmetric Multiprocessor Database Systems},
  booktitle = {18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA},
  date-modified = {2015-08-27 13:20:55 +0000},
  year = {2004},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2004.1302900},
  url = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2004.1302900},
  keywords = {jj-old},
  confidential = {n},
  abstract = {While excellent research results have been proposed for query optimization, little work has been done for the scheduling of query execution plans. This paper targets the optimization problem of the schedule lengths of query execution plans in a symmetric multiprocessor (SMP) database system. We show the NP-hardness of the optimization problem. A critical-path-based algorithm is proposed to minimize the schedule length of a collection of query execution plans. When each query execution plan has a tree or a directed acyclic graph structure, we show that the approximation ratios of our proposed algorithm are 2 and ($3 - 2^M$), respectively, where M is the number of processors in the system. When the proposed algorithm is adopted for online usages, the competitive ratio of the algorithm is proven being ($3 - 2^M$). The proposed algorithm is optimal when there is a suf.cient number of processors. The performance of the proposed algorithm is evaluated based on the TPC-C benchmark.},
}

@article { DBLP:journals/rts/ChenC13,
  author = {Chen, Jian-Jia and Chakraborty, Samarjit},
  title = {Resource augmentation for uniprocessor and multiprocessor partitioned scheduling of sporadic real-time tasks},
  journal = {Real-Time Systems},
  year = {2013},
  volume = {49},
  number = {4},
  pages = {475-516},
  url = {http://dx.doi.org/10.1007/s11241-013-9181-5},
  keywords = {jj-old},
  file = {http://link.springer.com/content/pdf/10.1007%2Fs11241-013-9181-5.pdf},
  confidential = {n},
  abstract = {Although the earliest-deadline-first (EDF) policy is known to be optimal for preemptive real-time task scheduling in uniprocessor systems, the schedulability analysis problem has recently been shown to be co NP-hard. Therefore, approximation algorithms, and in particular, approximations based on resource augmentation have attracted a lot of attention for both uniprocessor and multiprocessor systems. Resource augmentation based approximations assume a certain speedup of the processor(s). Using the notion of approximate demand bound function (dbf), in this paper we show that for uniprocessor systems the resource augmentation factor is at most $\frac{2e−1}{e}\approx 1.6322$, where e is the Euler number. We approximate the dbf using a linear approximation when the analysis interval length of interest is larger than the relative deadline of the task. For identical multiprocessor systems with M processors and constrained-deadline task sets, we show that the deadline-monotonic partitioning (that has been proposed by Baruah and Fisher) with the approximate dbf leads to an approximation factor of $\frac{3e−1}{e}−\frac{1}{M}\approx 2.6322−\frac{1}{M}$ with respect to resource augmentation. We also show that the corresponding factor is $3−\frac{1}{M}$ for arbitrary-deadline task sets. The best known results so far were $3−\frac{1}{M}$ for constrained-deadline tasks and $4−\frac{2}{M}$ for arbitrary-deadline ones. Our tighter analysis exploits the structure of the approximate dbf directly and uses the processor utilization violations (which were ignored in all previous analysis) for analyzing resource augmentation factors. We also provide concrete input instances to show that the lower bound on the resource augmentation factor for uniprocessor systems—using the above approximate dbf is 1.5, and the corresponding bound is 2.5 for identical multiprocessor systems with an arbitrary order of fitting and a large number of processors. Further, we also provide a polynomial-time approximation scheme (PTAS) to derive near-optimal solutions under the assumption that the ratio of the maximum relative deadline to the minimum relative deadline of tasks is a constant, which is a more relaxed assumption compared to the assumptions required for deriving such a PTAS in the past.},
}

@article { DBLP:journals/rts/YangBRCT13,
  author = {Yang, Hoeseok and Bacivarov, Iuliana and Rai, Devendra and Chen, Jian-Jia and Thiele, Lothar},
  title = {Real-time worst-case temperature analysis with temperature-dependent parameters},
  journal = {Real-Time Systems},
  year = {2013},
  volume = {49},
  number = {6},
  pages = {730-762},
  url = {http://dx.doi.org/10.1007/s11241-013-9188-y},
  keywords = {jj-old},
  confidential = {n},
  abstract = {With the evolution of today’s semiconductor technology, chip temperature increases rapidly mainly due to the growth in power density. Therefore, for modern embedded real-time systems it is crucial to estimate maximal temperatures early in the design in order to avoid burnout and to guarantee that the system can meet its real-time constraints. This paper provides answers to a fundamental question: What is the worst-case peak temperature of a real-time embedded system under all feasible scenarios of task arrivals? A novel thermal-aware analytic framework is proposed that combines a general event/resource model based on network and real-time calculus with system thermal equations. This analysis framework has the capability to handle a broad range of uncertainties in terms of task execution times, task invocation periods, jitter in task arrivals, and resource availability. The considered model takes both dynamic and leakage power as well as thermal dependent conductivity into consideration. Thorough simulation experiments validate the theoretical results.},
}

@article { DBLP:journals/corr/KaoCRW13,
  author = {Kao, Mong-Jen and Chen, Jian-Jia and Rutter, Ignaz and Wagner, Dorothea},
  date-modified = {2015-08-27 13:31:44 +0000},
  title = {Competitive Design and Analysis for Machine-Minimizing Job Scheduling Problem},
  journal = {CoRR},
  year = {2013},
  bdsk-url-1 = {http://arxiv.org/abs/1309.5697},
  volume = {abs/1309.5697},
  url = {http://arxiv.org/abs/1309.5697},
  keywords = {jj-old},
  confidential = {n},
  abstract = {We explore the machine-minimizing job scheduling problem, which has a rich history in the line of research, under an online setting. We consider systems with arbitrary job arrival times, arbitrary job deadlines, and unit job execution time. For this problem, we present a lower bound 2.09 on the competitive factor of \emph{any} online algorithms, followed by designing a 5.2-competitive online algorithm. We also point out a false claim made in an existing paper of Shi and Ye regarding a further restricted case of the considered problem. To the best of our knowledge, what we present is the first concrete result concerning online machine-minimizing job scheduling with arbitrary job arrival times and deadlines.},
}

@article { DBLP:journals/tsmc/LiSCL13,
  author = {Li, Jianjun and Shu, LihChyun and Chen, Jian-Jia and Li, Guohui},
  date-modified = {2015-08-27 13:31:56 +0000},
  title = {Energy-Efficient Scheduling in Nonpreemptive Systems With Real-Time Constraints},
  journal = {IEEE T. Systems, Man, and Cybernetics: Systems},
  year = {2013},
  bdsk-url-1 = {http://dx.doi.org/10.1109/TSMCA.2012.2199305},
  volume = {43},
  number = {2},
  pages = {332-344},
  url = {http://dx.doi.org/10.1109/TSMCA.2012.2199305},
  keywords = {jj-old},
  confidential = {n},
  abstract = {In the past decade, the development of mobile and embedded systems has demanded energy efficiency for improving the lifetime of embedded devices. To avoid preemption overhead or ease timing verification, nonpreemptive scheduling has been deemed useful or necessary in meeting system timing requirements for certain applications built on embedded devices. In this paper, our aim is to design nonpreemptive scheduling algorithms that ensure timing correctness and optimize energy consumption on a processor with variable speeds. We propose a representative algorithm, ISA, which can produce lower speeds for a variety of nonpreemptive task sets than other comparable methods, and hence resulting in significant energy savings. When combined with a selective frequency-inheritance policy we design to efficiently determine if processor speedup can be disabled without jeopardizing any task deadlines, ISA can achieve even larger gains, up to 30% reduction in energy consumption. Finally, we propose a dynamic slack reclamation policy built on ISA, namely ISA-DR, which can result in additional energy savings when a task consumes less than its worst-case execution time.},
}

@article { DBLP:journals/jise/ChenHT12,
  author = {Chen, Jian-Jia and Huang, Kai and Thiele, Lothar},
  date-modified = {2015-08-27 13:31:27 +0000},
  title = {Dynamic Frequency Scaling Schemes for Heterogeneous Clusters under Quality of Service Requirements},
  journal = {J. Inf. Sci. Eng.},
  year = {2012},
  bdsk-url-1 = {http://www.iis.sinica.edu.tw/page/jise/2012/201211_06.html},
  volume = {28},
  number = {6},
  pages = {1073-1090},
  url = {http://www.iis.sinica.edu.tw/page/jise/2012/201211_06.html},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Nowadays, both the performance and power consumption for modern server clusters and data centers must be considered to reduce the maintenance cost for quality of service guarantees, as power dissipation affects the cost of both the power delivery subsystems and colling facility. Considering the popularity of heterogeneous clusters, this paper proposes efficient and effective power management schemes for large scale server farms. Distinct from existing heuristic approaches, we propose dynamic frequency scaling schemes with approximation factor guarantees, compared to the optimal power management. By considering systems with discrete frequency levels on every server, our schemes can be applied for different power consumption models. Our greedy power management schemes have 1.5 or 2 approximation guarantees depending on the complexity. Our dynamic-programming approach can trade the quality, in terms of power consumption, of the resulting solutions with the time/space complexity. We provide extensive simulation results to show that the proposed schemes are effective for the minimization of the power consumption for large scale clusters.},
}

@article { DBLP:journals/tc/ChenYCC11,
  author = {Chen, Yi-Jung and Yang, Chia-Lin and Chi, Jaw-Wei and Chen, Jian-Jia},
  date-modified = {2015-08-27 13:31:00 +0000},
  title = {TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems},
  journal = {IEEE Trans. Computers},
  year = {2011},
  bdsk-url-1 = {http://doi.ieeecomputersociety.org/10.1109/TC.2011.44},
  volume = {60},
  number = {6},
  pages = {767-782},
  url = {http://doi.ieeecomputersociety.org/10.1109/TC.2011.44},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Existing leakage reduction techniques for hard real-time systems utilize slack to turn off a CPU completely. However, turning on/off a processor involves high performance and energy overheads. Hence, a hard real-time system is very likely to have unutilized slack if only the CPU shutdown technique is used to reduce leakage. Architectural-level shutdown techniques in all instances have a much lower overheads than turning off a CPU; therefore, they can be utilized in a hard real-time system to further reduce CPU leakage. However, existing architecture-level shutdown techniques cause unpredictable performance degradation thereby unsuitable for a hard real-time system that must meet the timing constraint in all cases. This paper is the first attempt to bridge this gap. This paper focuses on cache leakage reduction and proposes the first Timing-Aware Cache Leakage Control (TACLC) mechanism. TACLC exploits system slack to turn cache lines into low-leakage states provided that the timing constraint is met. The experimental results demonstrate that TACLC effectively utilizes system slack to reduce cache leakage. For systems with low CPU utilization, TACLC achieves comparable leakage reduction to the leakage control policy that aggressively turns cache lines into low-leakage modes while neglecting the timing constraint.},
}

@article { DBLP:journals/rts/HuangSCTB11,
  author = {Huang, Kai and Santinelli, Luca and Chen, Jian-Jia and Thiele, Lothar and Buttazzo, Giorgio C.},
  date-modified = {2015-08-27 13:30:34 +0000},
  title = {Applying real-time interface and calculus for dynamic power management in hard real-time systems},
  journal = {Real-Time Systems},
  year = {2011},
  bdsk-url-1 = {http://dx.doi.org/10.1007/s11241-011-9115-z},
  volume = {47},
  number = {2},
  pages = {163-193},
  url = {http://dx.doi.org/10.1007/s11241-011-9115-z},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Power dissipation has been an important design issue for a wide range of computer systems in the past decades. Dynamic power consumption due to signal switching activities and static power consumption due to leakage current are the two major sources of power consumption in a CMOS circuit. As CMOS technology advances towards deep sub-micron domain, static power dissipation is comparable to or even more than dynamic power dissipation. This article explores how to apply dynamic power management to reduce static power for hard real-time systems. We propose online algorithms that adaptively control the power mode of a system, procrastinating the processing of arrived events as late as possible. To cope with multiple event streams with different characteristics, we provide solutions for preemptive earliest-deadline-first and fixed-priority scheduling policies. By adopting a worst-case interval-based abstraction, our approach can not only tackle arbitrary event arrivals, e.g., with burstiness, but also guarantee hard real-time requirements with respect to both timing and backlog constraints. We also present extensive simulation results to demonstrate the effectiveness of our approaches.},
}

@article { DBLP:journals/jsa/ChenT11,
  author = {Chen, Jian-Jia and Thiele, Lothar},
  date-modified = {2015-08-27 13:30:45 +0000},
  title = {Platform synthesis and partitioning of real-time tasks for energy efficiency},
  journal = {Journal of Systems Architecture - Embedded Systems Design},
  year = {2011},
  bdsk-url-1 = {http://dx.doi.org/10.1016/j.sysarc.2010.09.008},
  volume = {57},
  number = {6},
  pages = {573-583},
  url = {http://dx.doi.org/10.1016/j.sysarc.2010.09.008},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy-efficient and power-aware designs have played important roles in modern computing systems to reduce the power bills for server systems or prolong the lifetime of embedded devices. Moreover, systems with multiple heterogeneous processing units have been widely adopted to enhance the computing capability or reduce the power consumption. This work explores how to synthesize a heterogeneous multiprocessor platform or select processing units with the partitioning of real-time tasks so that the energy consumption is minimized. Given a set of processing unit types, characterized by the power consumption for maintaining activeness and executing jobs, this paper proposes an efficient and effective algorithm to allocate processing units with energy-efficient task partitioning. When the constraint on the numbers of allocated processing units is not specified, we show that the algorithm is with a ($1+\ln n$)-approximation factor, in worst cases, for processing unit types with a variety of power consumption models, where n   is the number of tasks. The approximation factor is asymptotically optimal for polynomial-time approximation algorithms unless P=NP. Moreover, we also present how to deal with specified maximal numbers of allocated processing units to minimize the energy consumption. Simulation results show that the proposed algorithm is effective for energy consumption minimization.},
}

@article { DBLP:journals/jsa/FisherCWT11,
  author = {Fisher, Nathan and Chen, Jian-Jia and Wang, Shengquan and Thiele, Lothar},
  date-modified = {2015-08-27 13:31:03 +0000},
  title = {Thermal-aware global real-time scheduling and analysis on multicore systems},
  journal = {Journal of Systems Architecture - Embedded Systems Design},
  year = {2011},
  bdsk-url-1 = {http://dx.doi.org/10.1016/j.sysarc.2010.09.010},
  volume = {57},
  number = {5},
  pages = {547-560},
  url = {http://dx.doi.org/10.1016/j.sysarc.2010.09.010},
  keywords = {jj-old},
  confidential = {n},
  abstract = {As the power density of modern electronic circuits increases dramatically, systems are prone to overheating. Thermal management has become a prominent issue in system design. This paper explores thermal-aware scheduling for sporadic real-time tasks to minimize the peak temperature in a homogeneous multicore system, in which heat might transfer among some cores. By deriving an ideally preferred speed for each core, we propose global scheduling algorithms which can exploit the flexibility of multicore platforms at low temperature. We perform simulations to evaluate the performance of the proposed approach.},
}

@article { DBLP:journals/esticas/WangLCL11,
  author = {Wang, Shengquan and Liu, Jun and Chen, Jian-Jia and Liu, Xue},
  date-modified = {2015-08-27 13:30:51 +0000},
  title = {PowerSleep: A Smart Power-Saving Scheme With Sleep for Servers Under Response Time Constraint},
  journal = {IEEE J. Emerg. Sel. Topics Circuits Syst.},
  year = {2011},
  bdsk-url-1 = {http://dx.doi.org/10.1109/JETCAS.2011.2167532},
  volume = {1},
  number = {3},
  pages = {289-298},
  url = {http://dx.doi.org/10.1109/JETCAS.2011.2167532},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Reducing the power consumption while maintaining the response time constraint has been an important goal in server system design. One of the techniques widely explored in the literature to achieve this goal is dynamic voltage scaling (DVS). However, DVS is not efficient in modern systems where the overall power consumption includes a large portion of static power consumption. In this paper, we aim to reduce the static power consumption by dynamic power management (DPM) with sleep model in addition to DVS. To maximize the sleep efficiency, we propose PowerSleep, a smart power-saving scheme by carefully choosing an execution speed for the server with DVS and sleep periods while putting the system in the sleep power mode with DPM. By modeling the system with M/G/1/PS queuing model and further significant extensions, we present how to minimize the mean power consumption of the server under the given mean response time constraint. Simulation results show that our smart PowerSleep scheme significantly outperforms the simple power-saving scheme which adopts sleep mode.},
}

@article { DBLP:journals/vlsisp/LeeCS10,
  author = {Lee, Yung-Hen and Chen, Jian-Jia and Shih, Chi-Sheng},
  date-modified = {2015-08-27 13:29:53 +0000},
  title = {Energy-Efficient Considerations on a Variable-Bitrate PCI-Express Device},
  journal = {Signal Processing Systems},
  year = {2010},
  bdsk-url-1 = {http://dx.doi.org/10.1007/s11265-008-0280-9},
  volume = {59},
  number = {1},
  pages = {57-69},
  url = {http://dx.doi.org/10.1007/s11265-008-0280-9},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Dynamic power management has been adopted in many systems to reduce the power/energy consumption by changing the system state dynamically. This paper explores energy efficiency for systems equipped with PCI-Express devices, which are designed for low power consumption and high performance, compared to corresponding PCI devices. We propose dynamic power management mechanism and a management policy for energy-efficient considerations. A case study for a variable-bit-rate local-area-network device under the PCI-Express specification is exploited to provide supports for dynamic packet transmission. Simulation results show that the proposed mechanism and policy would reduce the system energy consumption substantially.},
}

@article { DBLP:journals/tii/SchranzhoferCT10,
  author = {Schranzhofer, Andreas and Chen, Jian-Jia and Thiele, Lothar},
  date-modified = {2015-08-27 13:29:46 +0000},
  title = {Dynamic Power-Aware Mapping of Applications onto Heterogeneous MPSoC Platforms},
  journal = {IEEE Trans. Industrial Informatics},
  year = {2010},
  bdsk-url-1 = {http://dx.doi.org/10.1109/TII.2010.2062192},
  volume = {6},
  number = {4},
  pages = {692-707},
  url = {http://dx.doi.org/10.1109/TII.2010.2062192},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Multiprocessor SOC platforms have been adopted for a wide range of high-performance applications, like automotive and avionic systems. Task assignment and processing unit allocation are key steps in the design of predictable and efficient embedded systems. Given the execution modes of applications, we propose a methodology to compute a task to processing element mapping, such that the expected average power consumption is minimized. Changing usage scenarios are represented by varying execution probabilities of modes. Statically precomputed template mappings for each execution probability are stored on the system and applied at runtime, allowing the system to adapt to changing environmental conditions. The underlying model considers static (leakage) and dynamic power. This study shows that deriving approximative solutions with a constant worst-case approximation factor in polynomial time is not achievable unless P = NP, even if a feasible task mapping is provided as an input. A polynomial-time heuristic algorithm is proposed that applies a multiple-step heuristic to derive template mappings. At runtime a manager monitors the system and chooses an appropriate precomputed template, hence low power-consumption is maintained over the systems lifetime. Experimental results reveal the effectiveness of the proposed algorithm by comparing the derived solutions to the optimal ones, obtained via an integer linear program (ILP).},
}

@article { DBLP:journals/jetc/MoserCT10,
  author = {Moser, Clemens and Chen, Jian-Jia and Thiele, Lothar},
  date-modified = {2015-08-27 13:29:28 +0000},
  title = {An energy management framework for energy harvesting embedded systems},
  journal = {JETC},
  year = {2010},
  bdsk-url-1 = {http://dx.doi.org/10.1145/1773814.1773818},
  volume = {6},
  number = {2},
  url = {http://dx.doi.org/10.1145/1773814.1773818},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Energy harvesting (also known as energy scavenging) is the process of generating electrical energy from environmental energy sources. There exists a variety of different energy sources such as solar energy, kinetic energy, or thermal energy. In recent years, this term has been frequently applied in the context of small autonomous devices such as wireless sensor nodes. In this article, a framework for energy management in energy harvesting embedded systems is presented. As a possible scenario, we focus on wireless sensor nodes that are powered by solar cells. We demonstrate that classical power management solutions have to be reconceived and/or new problems arise if perpetual operation of the system is required. In particular, we provide a set of algorithms and methods for various application scenarios, including real-time scheduling, application rate control, as well as reward maximization. The goal is to optimize the performance of the application subject to given energy constraints. Our methods optimize the system performance which, for example, allows the usage of smaller solar cells and smaller batteries. Furthermore, we show how to dimension important system parameters like the minimum battery capacity or a sufficient prediction horizon. Our theoretical results are supported by simulations using long-term measurements of solar energy in an outdoor environment. In contrast to previous works, we present a formal framework which is able to capture the performance, the parameters, and the energy model of various energy harvesting systems. We combine different viewpoints, include corresponding simulation results, and provide a thorough discussion of implementation aspects.},
}

@article { DBLP:journals/rts/ChuHTCK09,
  author = {Chu, Edward T.-H. and Huang, Tai-Yi and Tsai, Cheng-Han and Chen, Jian-Jia and Kuo, Tei-Wei},
  date-modified = {2015-08-27 13:26:39 +0000},
  title = {A DVS-assisted hard real-time I/O device scheduling algorithm},
  journal = {Real-Time Systems},
  year = {2009},
  bdsk-url-1 = {http://dx.doi.org/10.1007/s11241-009-9068-7},
  volume = {41},
  number = {3},
  pages = {222-255},
  url = {http://dx.doi.org/10.1007/s11241-009-9068-7},
  keywords = {jj-old},
  confidential = {n},
  abstract = {The I/O subsystem has become a major source of energy consumption in a hard real-time monitoring and control system. To reduce its energy consumption without missing deadlines, a dynamic power management (DPM) policy must carefully consider the power parameters of a device, such as its break-even time and wake-up latency, when switching off idle devices. This problem becomes extremely complicated when dynamic voltage scaling (DVS) is applied to change the execution time of a task. In this paper, we present COLORS, a composite low-power scheduling framework that includes DVS in a DPM policy to maximize the energy reduction on the I/O subsystem. COLORS dynamically predicts the earliest-access time of a device and switches off idle devices. It makes use of both static and dynamic slack time to extend the execution time of a task by DVS, in order to create additional switch-off opportunities. Task workloads, processor profiles, and device characteristics all impact the performance of a low-power real-time algorithm. We also identify a key metric that primarily determines its performance. The experimental results show that, compared with previous work, COLORS achieves additional energy reduction up to 20%, due to the efficient utilization of slack time.},
}

@article { DBLP:journals/rts/ChenWS06,
  author = {Chen, Jian-Jia and Wu, Jun and Shih, Chi-Sheng},
  date-modified = {2015-08-27 13:23:10 +0000},
  title = {Approximation algorithms for scheduling real-time jobs with multiple feasible intervals},
  journal = {Real-Time Systems},
  year = {2006},
  bdsk-url-1 = {http://dx.doi.org/10.1007/s11241-006-8198-4},
  volume = {34},
  number = {3},
  pages = {155-172},
  url = {http://dx.doi.org/10.1007/s11241-006-8198-4},
  keywords = {jj-old},
  confidential = {n},
  abstract = {Time-critical jobs in many real-time applications have multiple feasible intervals. Such a job is constrained to execute from start to completion in one of its feasible intervals. A job fails if the job remains incomplete at the end of the last feasible interval. Earlier works developed an optimal off-line algorithm to schedule all the jobs in a given job set and on-line heuristics to schedule the jobs in a best effort manner. This paper is concerned with how to find a schedule in which the number of jobs completed in one of their feasible intervals is maximized. We show that the maximization problem is NP-hard for both non-preemptible and preemptible jobs. This paper develops two approximation algorithms for non-preemptible and preemptible jobs. When jobs are non-preemptible, Algorithm Least Earliest Completion Time First (LECF) is shown to have a 2-approximation factor; when jobs are preemptible, Algorithm Least Execution Time First (LEF) is proved being a 3-approximation algorithm. We show that our analysis for the two algorithms are tight. We also evaluate our algorithms by extensive simulations. Simulation results show that Algorithms LECF and LEF not only guarantee the approximation factors but also outperform other multiple feasible interval scheduling algorithms in average.},
}