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2009 EDAA PhD Forum at DATE in Nice

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Peter Marwedel
Chair 2009 EDAA/DATE PhD Forum

PhD Forum Committee

  • P. Marwedel (Chair), TU* Dortmund, Germany
  • N. When, TU* Kaiserslautern, Germany
  • N. Dutt, University of California, Irvine, USA
  • D. Bertozzi, University of Bologna, Italy
  • J. Figueras, Departament d‘Enginyeria Electrònica, Barcelona, Spain
  • W. Anheier, Bremen University, Germany
  • T. Vierhaus, TU* Cottbus, Germany
  • M. Balakrishnan, Indian Institute of Technology, Delhi India
  • J. Henkel, University of Karlsruhe, Germany
  • U. Heinkel, TU* Chemnitz, Germany
  • C. Bobda, University of Potsdam, Germany
  • U. Rückert, University of Paderborn, Germany
  • B. Lisper, University College of Mälardalen, Sweden
  • P. Puschner, TU* Wien, Austria
  • L. Thiele, Laboratory TIK, ETH Zurich, Switzerland
  • S. Stuijk, TU* Eindhoven, Netherlands,
  • R. Ernst, TU*Braunschweig, Germany

* TU = Technical University

Selected presentations

  1. Herter, Joerg, Saarland University, Germany, »Precise WCET Analysis in the Presence of Dynamic Memory Allocation«
  2. Reineke, Jan, Saarland University, Germany, »Predictability of Cache Replacement Policies«
  3. Bordoloi, Unmesh, National University Singapore, »Interactive Design Space Exploration of Real-Time Embedded Systems«
  4. Banerjee, Pritha, Indian Statistical Institute Kolkata, India, »Faster Placement and Floorplanning in FPGAs«
  5. Heirman, Wim, Ghent University, Belgium, »Reconfigurable Optical Interconnection Networks for Shared-Memory Multiprocessor Architectures«
  6. Göhringer, Diana, FGAN-FOM, Ettlingen, Germany, »Multi-Processor-based High Performance Computing utilizing dynamic reconfigurable Hardware»
  7. Alsayeg, Khaled, TIMA Laboratory, Grenoble, France, »Direct mapping of sequential QDI controllers«
  8. Rashid, Muhammad, Thomson Research, Cesson Sevigne, France »Design Space Exploration in Heterogeneous Embedded Systems«
  9. Kumar, Akash, University of Technology, Eindhoven, Netherlands, »Analysis, Design and Management of Multimedia Multiprocessor Systems«
  10. Tisan, Alin, North University Maia Mare, Romania, »Contributions to the analysis, synthesis and implementation of applications with intelligent sensorial systems: The electronic nose«
  11. Lipskoch, Henrik, Carl-von-Ossietzky University, Oldenburg, Germany, »Optimisation of battery operating life considering software tasks and their timing behaviour«
  12. Liu, Qiang, Imperial College, London, UK, »Data Reuse and Parallelism in Hardware Compilation«
  13. Devos, Harald, Ghent University, Belgium, »Loop Transformations for the Optimized Generation of Reconfigurable Hardware«
  14. Moser, Clemens, Institute TIK, Zurich, Switzerland, »Performance Optimization in Energy Harvesting Embedded Systems«
  15. Keinert, Joachim, Fraunhofer Institute, Erlangen, Germany, »Data Flow Based System Level Design and Analysis of Image Processing Applications«
  16. Campos Costa, Jose Carlos, INESC-ID, Lissabon, Portugal, »Coverage-Directed Observability-Based Validation Method for Embedded Software«
  17. Lokuciejewski, Paul, University of Technology Dortmund, Germany, »WCET-aware Source Code and Assembly Level Optimization Techniques for Time Critical Systems»
  18. Boncalo, Oana, University of Timisoara, Romania, »Simulation Based Reliability Assessment of Quantum Circuits«
  19. Hansson, Andreas, University of Technology, Eindhoven, Netherlands, »A Predictable and Composable On-Chip Interconnect«
  20. Loi, Igor, University of Bologna, Italy »Synthesis of Low-Overhead Configurable Source Routing Tables for Network Interfaces«
  21. Akesson, Benny, University of Technology, Eindhoven, Netherlands, »Designing Real-Time Systems-on-Chip Using Predictable and Composable System Services«
  22. Prasad das, Bishnu, Institute of Science, Bangalore, India, »Delay Variability: Modeling and On-chip Measurement«
  23. Fossati, Luca, Dipartimento di Elettronica e Informazione, Milano, Italy, »Optimization and Design Space Exploration of MPSoCs«
  24. Marongiu, Andrea, University of Bologna, Italy, »OpenMP Support for MPSoCs with Explicitly Managed Memory Hierarchy«
  25. Bartolini, Andrea, University of Bologna, Italy, »DBS4video: Dynamic Luminance Backlight Scaling based on Multi-Histogram Frame Characterization for Video Streaming Application«
  26. Beyrouthy, Taha, TIMA laboratory, Grenoble, France, »Secure Asynchronous FPGA for embedded systems«
  27. Rogin, Frank, Fraunhofer Institute, Dresden, Germany, »An Integrated Approach to Utilize Designer‘s Debug Capacity in System-on-a-Chip Designs«
  28. Klemm, Reimund, University of Technology, Dresden, Germany, »A Processor Architecture and Compiler for Bitstream Processing«
  29. Eggersgluess, Stephan, Bremen University, Germany, »Robust Algorithms for High Quality Test Pattern Generation using Boolean Satisfiability«
  30. Medardoni, Simone, University of Ferrara, Italy, »Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints«
  31. Murillo, Jaime Joven, Barcelona University , Spain, »A lightweight MPI-based programming model and its HW support for NoC-based MPSoCs«
  32. Courtay, Antoine, LabSTICC, Lorient, France, »On-On-chip interconnects energy consumption: High-level estimation and architectural optimizations«
  33. Di Guglielmo, Giuseppe, University of Verona, Italy, »On the Validation of Embedded Systems through Functional ATPG«
  34. Lallet, Julien, IRISA-ENSSAT, Lannion, France, »Mozaïc : generic framework for modeling and design of dynamically reconfigurable architectures«
  35. Ruggiero, Martino, University of Bologna, Italy, »Cellflow: a Parallel Application Development Environment with RunTime Support for the Cell BE Processor«
  36. Modarressi, Mehdi, Sharif University, Teheran, Iran, »A Hybrid Packet-Switched and Circuit-Switched On-Chip Network Based on Spatial-Division Multiplexing«
  37. Schliecker, Simone, Technical University Braunschweig, Germany, »Performance Analysis for Multiprocessor Systems-On-Chip«
  38. Paci, Ciacomo, University of Bologna, Italy, »How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design«
  39. Palla, Murthy, Bremen University, Germany, »Reduction of Crosstalk Pessimism with the consideration of logic and timing correlations«
  40. Petersén, Kim, KTH/ICT/ECS Kista, Sweden, »A highly scalable and (almost) c-testable BIST for NoCS«
  41. Rana, Vincenzo, Milano University, Italy, »A Reconfigurable NoC-based Communication Infrastructure for Multi-Processor SoCs«
  42. Roessler, Marko, Technical University Chemnitz, Germany, »Parallel Hardware- and Software Threads in a Dynamically Reconfigurable System on a Programmable Chip»
  43. Baloukas, Christos, University of Thrace, Greece, »Data structures optimization methodology of Dynamic Applications in Embedded Systems«
  44. Bertels, Peter, University of Gent, Belgium, »Analysing Communication Leads to More E cient Systems«
  45. Garg, Siddharth, Carnegie Mellon University, Pittsburgh, Pennsylvania, US, »Variability Analysis and Mitigation at the System Level«
  46. Kuo, Chin-Cheng, University of Taiwan, Taiwan, »Efficient Bottom-up Approaches to Build Variation-aware PLL Behavioral Models«
  47. Golshan, Shahin, University of California, US, »Novel Algorithms to Mitigate Soft Errors in SRAM-based Programmable Systems«