@techreport { Weichert:2010c,
  author = {Weichert, Frank and Gaspar, Marcel and Timm, Constantin and Zybin, Alexander and Gurevich, Evgeny and Engel, Michael and M{\"u}ller, Heinrich and Marwedel, Peter},
  title = {Signal Analysis and Classification for Plasmon Assisted Microscopy of Nanoobjects},
  institution = {TU Dortmund, Faculty of Computer Science 12},
  year = {2010},
  number = {830},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-weichertTR830.pdf},
  confidential = {n},
  abstract = {In this paper we suggest a novel technique for surface plasmon resonance assisted detection of viruses and nanoparticles which can be applied for rapid analysis of large data volumes. The future availability of such an efficient detection method for viruses is evident in terms of globally spreading virus infections. The technique is based on the segmentation of slices, aimed at an automatic identification of nanoparticles, in which detection is based on positionstationary spatiotemporal data using a one dimensional signal-analysis and -classification approach. As data source a CCD camera taking a sequence of snapshots from a surface plasmon assisted microscopy is used. A one dimensional intensity analysis approach is applied for segmentation by classifying time dependent 1D gray level profiles and combining them into spatial 2D segments.},
}

@techreport { Timm:2010,
  author = {Timm, Constantin and Gelenberg, Andrej and Weichert, Frank and Marwedel, Peter},
  title = {Reducing the Energy Consumption of Embedded Systems by Integrating General Purpose GPUs},
  institution = {TU Dortmund, Faculty of Computer Science 12},
  year = {2010},
  number = {829},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-timmTR829.pdf},
  confidential = {n},
  abstract = {Nowadays, General Purpose Computing on GPUs (GPGPU) accelerates many industrial and scientific applications in the high performance computing (HPC) domain. Recently, GPU vendors, such as Nvidia and AMD, promoted the utilization of high end GPUs in embedded systems. The intention of the GPU vendors is the acceleration of traditional graphics computations, but in analogy to the HPC desktop domain, GPUs could also be used as GPGPU in the embedded domain. However, energy constraints are omnipresent in the embedded world and therefore, one central question for embedded system designers is: Can energy be saved by using an additional GPGPU-equipped graphics card to accelerate general purpose applications? This paper firstly discusses the theoretical background of an energy aware embedded system design including a GPGPU-equipped graphics card. In order to support these theoretical considerations, secondly an energy and runtime evaluation of a low power GPU/CPU system is presented. We demonstrate that a profitable GPU integration, seen from an energy perspective, strongly depends on the structure and the features of an application such as a high parallelizability and the utilization level of the graphics card. The evaluation of several real world benchmarks shows that increasing the system’s power consumption by integrating a GPU can lead to a reduced overall energy consumption of a system.},
}

@inproceedings { marwedel:10:GI,
  author = {Marwedel, Peter and Engel, Michael},
  title = {Plea for a Holistic Analysis of the Relationship between Information Technology and Carbon-Dioxide Emissions},
  booktitle = {Workshop on Energy-aware Systems and Methods (GI-ITG)},
  year = {2010},
  address = {Hanover / Germany},
  month = {feb},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/arcs-10-marwedel.pdf},
  confidential = {n},
  abstract = {An analysis of the relationship between information technology (IT) and carbon-dioxide (CO2) emissions should not be constrained to an analysis of emissions caused during the operation of IT equipment. Rather, an analysis of emissions should be based on a full life-cycle assessment (LCA) of IT systems, from their conception until their recycling. Also, the reduction of emissions through the use of IT systems should not be forgotten. This paper explains these viewpoints in more detail and provides rough life-cycle analyses of personal computers (PCs). It will be shown that|for standard scenarios|emissions from PC production are exceeding those of their shipment and use. This stresses the importance of using PCs as long as possible.},
}

@inproceedings { timm:2010:adpc,
  author = {Timm, Constantin and Gelenberg, Andrej and Marwedel, Peter and Weichert, Frank},
  title = {Energy Considerations within the Integration of General Purpose GPUs in Embedded Systems},
  booktitle = {Proceedings of the International Conference on Advances in Distributed and Parallel Computing},
  year = {2010},
  month = {November},
  publisher = {Global Science \& Technology Forum},
  confidential = {n},
}

@inproceedings { cordes:10:CODES,
  author = {Cordes, Daniel and Marwedel, Peter and Mallik, Arindam},
  title = {Automatic Parallelization of Embedded Software Using Hierarchical Task Graphs and Integer Linear Programming},
  booktitle = {Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (CODES+ISSS 2010)},
  year = {2010},
  address = {Scottsdale / US},
  month = {oct},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-codes-cordes.pdf},
  confidential = {n},
  abstract = {The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using multiple cores in a single system enables to close the gap between energy consumption, problems concerning heat dissipation, and computational power. Nevertheless, these benefits do not come for free. New challenges arise, if existing applications have to be ported to these multiprocessor platforms. One of the most ambitious tasks is to extract efficient parallelism from these existing sequential applications. Hence, many parallelization tools have been developed, most of them are extracting as much parallelism as possible, which is in general not the best choice for embedded systems with their limitations in hardware and software support. In contrast to previous approaches, we present a new automatic parallelization tool, tailored to the particular requirements of the resource constrained embedded systems. Therefore, this paper presents an algorithm which automatically steers the granularity of the generated tasks, with respect to architectural requirements and the overall execution time reduction. For this purpose, we exploit hierarchical task graphs to simplify a new integer linear programming based approach in order to split up sequential programs in an efficient way. Results on real-life benchmarks have shown that the presented approach is able to speed sequential applications up by a factor of up to 3.7 on a four core MPSoC architecture.},
}

@inproceedings { marwedel:10:VDE,
  author = {Marwedel, Peter and Engel, Michael},
  title = {Ein Pl{\"a}doyer f{\"u}r eine holistische Analyse der Zusammenh{\"a}nge zwischen Informationstechnologie und Kohlendioxyd-Emissionen},
  booktitle = {VDE-Kongress},
  year = {2010},
  address = {Leipzig, Germany},
  month = {nov},
  confidential = {n},
}

@inproceedings { plazar:10:isbis,
  author = {Plazar, Sascha and Marwedel, Peter and Rahnenf\ührer, J\örg},
  title = {Optimizing Execution Runtimes of R Programs},
  booktitle = {Book of Abstracts of International Symposium on Business and Industrial Statistics (ISBIS)},
  year = {2010},
  pages = {81-82},
  address = {Portoroz (Portorose) / Slovenia},
  month = {jul},
  keywords = {rcs},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-isbis.pdf},
  confidential = {n},
}

@inproceedings { plazar:10:isorc,
  author = {Plazar, Sascha and Lokuciejewski, Paul and Marwedel, Peter},
  title = {WCET-driven Cache-aware Memory Content Selection},
  booktitle = {Proceedings of the 13th IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC)},
  year = {2010},
  pages = {107-114},
  address = {Carmona / Spain},
  month = {may},
  keywords = {wcet},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-isorc.pdf},
  confidential = {n},
  abstract = {Caches are widely used to bridge the increasingly growing gap between processor and memory performance. They store copies of frequently used parts of the slow main memory for faster access.  Static analysis techniques allow the estimation of the worst-case cache behavior and enable the computation of an upper bound of the execution time of a program. This bound is called worst-case execution time (WCET). Its knowledge is crucial to verify if hard real-time systems satisfy their timing constraints and the WCET is a key parameter for the design of embedded systems.  In this paper, we propose a new WCET-driven cache-aware memory content selection algorithm, which allocates functions whose WCET highly benefits from a cached execution to cached memory areas. Vice versa, rarely used functions which do not benefit from a cached execution are allocated to non-cached memory areas. As a result of this, unfavorable functions w.\,r.\,t. a program's WCET can not evict beneficial functions from the cache. This can lead to a reduced cache miss ratio and a decreased WCET. The effectiveness of our approach is demonstrated by results achieved on real-life benchmarks. In a case study, our greedy algorithm is able to reduce the benchmarks' WCET by up to 20\%.},
}

@inproceedings { weichert:10:bvm,
  author = {Weichert, Frank and Gaspar, Marcel and Zybin, Alexander and Gurevich, Evgeny and G\"ortz, Alexander and Timm, Constantin and M\"uller, Heinrich and Marwedel, Peter},
  title = {Plasmonen-unterst\"utzte Mikroskopie zur Detektion von Viren},
  booktitle = {Bildverarbeitung f\"ur die Medizin},
  year = {2010},
  address = {Aachen / Germany},
  month = {March},
  confidential = {n},
  abstract = {In Anbetracht zunehmend epidemisch auftretender viraler Infektionen ist eine effiziente und ubiquit\"ar verf\"ugbare Methode zur sicheren Virusdetektion hoch relevant. Mit der Plasmonen-unterst\"utzten Mikroskopie steht hierzu eine neuartige Untersuchungsmethode bereit, die aber gro\"se Anforderungen an die Bildverarbeitung zur Differenzierung der Viren innerhalb der Bilddaten stellt. In dieser Arbeit wird hierzu ein erster erfolgversprechender Ansatz vorgestellt. \"Uber bildbasierte Mustererkennung und Zeitreihenanalysen in Kombination mit Klassifikationsverfahren konnte sowohl die Differenzierung von Nanoobjekten als auch die Detektion von Virus-\"ahnlichen Partikeln nachgewiesen werden.},
}

@inproceedings { heinig:10:hotdep,
  author = {Heinig, Andreas and Engel, Michael and Schmoll, Florian and Marwedel, Peter},
  title = {Using Application Knowledge to Improve Embedded Systems Dependability},
  booktitle = {Proceedings of the Workshop on Hot Topics in System Dependability (HotDep 2010)},
  year = {2010},
  address = {Vancouver, Canada},
  month = {oct},
  publisher = {USENIX Association},
  keywords = {ders},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-heinig-hotdep.pdf},
  confidential = {n},
}

@inproceedings { heinig:10:estimedia,
  author = {Heinig, Andreas and Engel, Michael and Schmoll, Florian and Marwedel, Peter},
  title = {Improving Transient Memory Fault Resilience of an H.264 Decoder},
  booktitle = {Proceedings of the Workshop on Embedded Systems for Real-time Multimedia (ESTIMedia 2010)},
  year = {2010},
  address = {Scottsdale, AZ, USA},
  month = {oct},
  publisher = {IEEE Computer Society Press},
  keywords = {ders},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-heinig-estimedia.pdf},
  confidential = {n},
}

@inproceedings { lokuciejewski:10:icess,
  author = {Lokuciejewski, Paul and Kelter, Timon and Marwedel, Peter},
  title = {Superblock-Based Source Code Optimizations for WCET Reduction},
  booktitle = {Proceedings of the 7th International Conference on Embedded Software and Systems (ICESS)},
  year = {2010},
  pages = {1918-1925},
  address = {Bradford / UK},
  month = {jun},
  keywords = {wcet},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-icess.pdf},
  confidential = {n},
  abstract = {Superblocks represent regions in a program code that consist of multiple basic blocks. Compilers benefit from this structure since it enables optimization across block boundaries. This increased optimization potential was thoroughly studied in the past for average-case execution time (ACET) reduction at assembly level.  In this paper, the concept of superblocks is exploited for the optimization of embedded real-time systems that have to meet stringent timing constraints specified by the worst-case execution time (WCET). To achieve this goal, our superblock formation is based on a novel trace selection algorithm which is driven by WCET data. Moreover, we translate superblocks for the first time from assembly to source code level. This approach enables an early code restructuring in the optimizer, providing more optimization opportunities for both subsequent source code and assembly level transformations. An adaption of the traditional optimizations common subexpression and dead code elimination to our WCET-aware superblocks allows an effective WCET reduction. Using our techniques, we significantly outperform standard optimizations and achieve an average WCET reduction of up to 10.2\% for a total of 55 real-life benchmarks.},
}

@inproceedings { lokuciejewski:10:isorc,
  author = {Lokuciejewski, Paul and Plazar, Sascha and Falk, Heiko and Marwedel, Peter and Thiele, Lothar},
  title = {Multi-Objective Exploration of Compiler Optimizations for Real-Time Systems},
  booktitle = {Proceedings of the 13th International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC)},
  year = {2010},
  pages = {115-122},
  address = {Carmona / Spain},
  month = {may},
  keywords = {wcet},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-isorc_2.pdf},
  confidential = {n},
  abstract = {With the growing complexity of embedded systems software, high code quality can only be achieved using a compiler. Sophisticated compilers provide a vast spectrum of various optimizations to improve code aggressively w.r.t. different objective functions, e.g., average-case execution time \textit{(ACET)} or code size. Due to the complex interactions between the optimizations, the choice for a promising sequence of code transformations is not trivial. Compiler developers address this problem by proposing standard optimization levels, e.g., \textit{O3} or \textit{Os}. However, previous studies have shown that these standard levels often miss optimization potential or might even result in performance degradation.  In this paper, we propose the first adaptive WCET-aware compiler framework for an automatic search of compiler optimization sequences which yield highly optimized code. Besides the objective functions ACET and code size, we consider the worst-case execution time \textit{(WCET)} which is a crucial parameter for real-time systems. To find suitable trade-offs between these objectives, stochastic evolutionary multi-objective algorithms identifying Pareto optimal solutions are exploited. A comparison based on statistical performance assessments is performed which helps to determine the most suitable multi-objective optimizer. The effectiveness of our approach is demonstrated on real-life benchmarks showing that standard optimization levels can be significantly outperformed.},
}

@inproceedings { lokuciejewski:10:smart,
  author = {Lokuciejewski, Paul and Stolpe, Marco and Morik, Katharina and Marwedel, Peter},
  title = {Automatic Selection of Machine Learning Models for WCET-aware Compiler Heuristic Generation},
  booktitle = {Proceedings of the 4th Workshop on Statistical and Machine Learning Approaches to Architectures and Compilation (SMART)},
  year = {2010},
  pages = {3-17},
  address = {Pisa / Italy},
  month = {jan},
  keywords = {wcet},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-smart.pdf},
  confidential = {n},
  abstract = {Machine learning has shown its capabilities for an automatic generation of heuristics used by optimizing compilers. The advantages of these heuristics are that they can be easily adopted to a new environment and in some cases outperform hand-crafted compiler optimizations. However, this approach shifts the effort from manual heuristic tuning to the model selection problem of machine learning - i.e., selecting learning algorithms and their respective parameters - which is a tedious task in its own right.  In this paper, we tackle the model selection problem in a systematic way. As our experiments show, the right choice of a learning algorithm and its parameters can significantly affect the quality of the generated heuristics. We present a generic framework integrating machine learning into a compiler to enable an automatic search for the best learning algorithm. To find good settings for the learner parameters within the large search space, optimizations based on evolutionary algorithms are applied. In contrast to the majority of other approaches aiming at a reduction of the average-case execution time (ACET), our goal is the minimization of the worst-case execution time (WCET) which is a key parameter for embedded systems acting as real-time systems. A careful case study on the heuristic generation for the well-known optimization loop invariant code motion shows the challenges and benefits of our methods.},
}

@inproceedings { pyka:2010,
  author = {Pyka, Robert and Klein, Felipe and Marwedel, Peter and Mamagkakis, Stylianos},
  title = {Versatile System-Level Memory-Aware Platform Description Approach for Embedded MPSoCs},
  booktitle = {Proc. of the ACM SIGPLAN/SIGBED 2010 Conference on Languages, Compilers, and Tools for Embedded Systems},
  year = {2010},
  pages = {9-16},
  publisher = {ACM},
  confidential = {n},
  abstract = {In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previous system modeling approaches this approach tries to model the whole system and especially the memory hierarchy in a structural and semantically accessible way. Previous approaches primarily support generation of simulators or retargetable code selectors and thus concentrate on pure behavioral models or describe only the processor instruction set in a semantically accessible way, A simple, database-like, interface is offered to the optimization developer, which in conjunction with the MACCv2 framework enables rapid development of source-level architecture independent optimizations.},
}

@misc { marw:10:hipeac,
  author = {Marwedel, Peter},
  title = {Software-based Flexible Fault Tolerance for Embedded Real-time Systems.},
  howpublished = {presentation},
  year = {2010},
  note = {2nd hipeac workshop on design for predictability},
  confidential = {n},
}

@misc { cordes:10:depcp,
  author = {Cordes, Daniel and Marwedel, Peter},
  title = {An automatic parallelization tool for embedded systems, based on hierarchical task graphs},
  month = {mar},
  year = {2010},
  note = {Research Poster at The Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP'2010) (DATE Workshop)},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-cordes-depcp.pdf},
  confidential = {n},
  abstract = {The last years have shown that there is no way to neglect the advan- tages provided by multi core systems. Using multiple cores in a single system enables to close the gap between energy consumption, problems concerning temperature deployment, and computational power. The most functional implementations for embedded systems are written in sequen- tial ANSI-C code to be executed on a single core embedded processor. Unfortunately, it is not possible to just change the underlying hardware platform, recompile the code and retrieve an emissionscient executable application. Many new challenges appear if existing systems are ported to MPSoC platforms. The process of manually converting sequential code is an error-prone and extremely time consuming task. As a consequence, the burden of generating parallel code should be shifted from the designer to an automatic tool, so that he is able to focus at the main part of modeling the behavior of his system. Such a tool should be presented in this work. It is an automatic parallelization tool which combines the advantages of hierarchical task graphs and integer linear programming systems to split up a sequential program into tasks in a fully automatic manner.},
}

@misc { marw-falk:10:cpsweek,
  author = {Marwedel, Peter and Falk, Heiko},
  title = {Reconciling compilers and timing analysis (Invited Talk)},
  month = {apr},
  year = {2010},
  keywords = {wcet},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2010-cpsweek-industrialworkshop.pdf},
  confidential = {n},
  abstract = {Most embedded/cyber-physical systems have to respect timing constraints. Ensuring meeting such constraints is currently typically based on a trial-and-error procedure involving many time-consuming software generation attempts. In this talk, we will demonstrate how the integration of timing analysis into a compiler for an automotive processor can provide a systematic path toward optimized worst-case execution times and can cut down costs.},
}

@book { lokuciejewski:10:springer,
  author = {Lokuciejewski, Paul and Marwedel, Peter},
  title = {Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems},
  publisher = {Springer},
  year = {2010},
  month = {nov},
  keywords = {wcet},
  confidential = {n},
  abstract = {For real-time systems, the worst-case execution time (WCET) is the key objective to be considered. Traditionally, code for real-time systems is generated without taking this objective into account and the WCET is computed only after code generation. \textit{Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems} presents the first comprehensive approach integrating WCET considerations into the code generation process. Based on the proposed reconciliation between a compiler and a timing analyzer, a wide range of novel optimization techniques is provided. Among others, the techniques cover source code and assembly level optimizations, exploit machine learning techniques and address the design of modern systems that have to meet multiple objectives.  Using these optimizations, the WCET of real-time applications can be reduced by about 30\% to 45\% on the average. This opens opportunities for decreasing clock speeds, costs and energy consumption of embedded processors. The proposed techniques can be used for all types real-time systems, including automotive and avionics IT systems.},
}

@article { weichert:2010:sensoractuators,
  author = {Weichert, Frank and Gaspar, Marcel and Timm, Constantin and Zybin, Alexander and Gurevich, Evgeny and Engel, Michael and M{\"u}ller, Heinrich and Marwedel, Peter},
  title = {Signal Analysis and Classification for Surface Plasmon Assisted Microscopy of Nanoobjects},
  journal = {Sensors and Actuators B: Chemical, Elsevier},
  year = {2010},
  volume = {151},
  pages = {281-290},
  confidential = {n},
}