The component "cacheprotocol" demonstrates, how the MESI protocol can be used as a multi-processor cache coherence protocol by visualizing the dynamic process of the MESI protocol. The component represent a multi-processor system with a shared memory, four processors, their corresponding caches and a snooping bus. Visualizing the dynamic process of the protocol means that depending on different read and write requests of the processors the component shows the signal and data transfers between the individual caches and the memory. Moreover it visualizes the state transitions of the addressed cache blocks. In illustration 1 you can see a picture of the component structure.
The Modified-Exclusive-Shared-Invalid (MESI) protocol is an example for a write invalidate protocol and ensures the cache coherence in a multi-processor system. The realized protocol process of the component is based on the protocol description in chaper 9 of the book "Computer Organization & Design, The Hardware/Software Interface " from Hennessy & Patterson. For a visualization of the cache state transitions of the MESI protocol please have a look to the RaVi component "mesi".
The book of Hennessy & Patterson quotes no special hardware structure for the implementation of the MESI protocol. For learning the basic concepts of the protocol we have decided to visualizes the MESI protocol process and therefore we have described the elements on a higher abstraction level. Only that kind of behavior is specified by the component which is necessary for the process of the protocol. Additional functionality, for example of the cache memories or the processors, is not implemented. At this point it is important to mention, that the structure described in this component is not a complete hardware structure for the implementation of the MESI protocol.
![]() Illustration 1: Structure of the Component "cacheprotocol" |
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The illustration above shows the structure of the component. At the top you can see the four processors of the multi-processor system. Within the icon of each processor a memory buffer is displayed. This memory buffer is addressed whenever the processor issues a read or a write request. |