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the MIPS Instruction Subset

Below you find the MIPS instruction subset which is implemented by the pipeline components. The subset includes all instructions of the main group and all instructions with opcode "00".

The formats of the instructions are mainly the same as described in the book of Hennessy & Patterson ("Computer Organizition and Design", appendix A.10). The particular variations of the formats are specified here.

Arithmetic and Logical Instructions

add - Addition (with overflow)
addu - Addition (without overflow)
addi - Addition immediate (with overflow)
addiu - Addition immediate (without overflow)
and - AND
andi - AND immediate
div - Divide (with overflow)
divu - Divide (without overflow)
mult - Multiply
multu - Unsigned multiply
nor - NOR

or - OR
ori - OR immediate
sll - Shift left logical
sra - Shift right arithmetic
srav - Shift right arithmetic variable
srl - Shift right logical
srlv - Shift right logical variable
sub - Subtract (with overflow)
subu - Subtract (without overflow)
xor - Exclusive OR
xori - XOR immediate

Variations of format
mult rd, rs, rt
0 rs rt rd 0 0x18
6 5 5 5 5 6
div rd, rs, rt
0 rs rt rd 0 0x1a
6 5 5 5 5 6

Comparison Instructions

slt - Set less than
sltu - Set less than unsigned
slti - Set less than immediate
sltiu - Set less than unsigned immediate

Branch Instructions
(only "pipeline3" component)

beq - Branch on equal
bgtz - Branch on greater than zero
blez - Branch on less than equal zero
bne - Branch on not equal

Store Instructions

sb - Store byte
sh - Store halfword
sw - Store word
swcz - Store word coprocessor z(0-3)
swl - Store word left
swr - Store word right

Data Movement Instructions

mfhi - Move from hi
mflo - Move from lo
mthi - Move to hi
mtlo - Move to lo

Constant-Manipulating Instructions

lui - Load upper immediate

Exception and Interrupt Instructions

syscall - System call
break - Break

Jump Instructions
(only "pipeline4" component)

j - Jump
jal - Jump and link
jalr - Jump and link register
jr - Jump register

Load Instructions

lb - Load byte
lbu - Load unsigned byte
lh - Load halfword
lhu - Load unsigned halfword
lw - Load word
lwcz - Load word coprocessor z(0-3)
lwl - Load word left
lwr - Load word right