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Department of Computer Science 12


Visualization of Computer Architecture (RaVi)

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Cacheprotocol

Visualization Control | Edit Memory and Processor Content | Documentation "cacheprotocol" | Component "mesi"

The following text explains the control and interaction of the component "cacheprotocol". By a clicking on the right icon you can start "cacheprotocol". If everything works alright, an additional window will be opened with the loaded component and you can give it a try directly here.

Certainly you can start the RaVi system on your computer and you can load the component "cacheprotocol". Loading the component means to open the subdesign file "cacheprotocol.hds" in the RaVi directory. For further information about system start and loading a component please have a look to the page Starting RaVi System - Loading a RaVi Component

After successfully loading the component "cacheprotocol" you will see the structure of the component like the one shown in the illustraction 1. All data and signal lines are undefined (light blue colored). All read and write switches are disabled (light blue or grey colored) and the memory line of each processor applies to the address 0 of the memory and contains the default start value of "00000000000000000". For a detail description of the structure please have a look to the documentation page of this component.
The submenu and the hyperlinks give further information

Illustration 1: The component "cacheprotocol"

Visualization Control

For starting the application flow of the component you have to click on the switch "step". The switch "step" represents a manual clock signal and every push on it corresponds to a single clock transition. The colors "grey" and "red" represent the signal values '0' and '1'. Every edge of the clock "step" let the component goes on with the next step of the visualization.

Illustration 2: First Step of a Read Request

The user can issue a read or a write request of a processor by using the switch "read" or "write" at the top of the processor icon. A read request for example is issued, if the switch "read" has the ouput value '1' (red colored). Therefor the user must push the switch "read" of the selected processor. For viewing the resulting data and signal transfers some pushs on the switch "step" have to follow. Illustration 2 above shows the first visualization step of a read request.

Illustration 3: Resulting Step of a Read Request

Illustration 3 shows the resulting step of a read request. After some visualizations steps the selected processor and its cache are contains the current value of the memory buffer 0. The corresponding cache line has got the state value "01" which stands for the state "exclusive".

Before the next request could be started, the user must disable the processor request manually. This can be done by another push on the switch "read" . The read request is disabled for example, if the switch has the output value '0' (grey colored).

Edit Memory and Processor Content

Editing the processor and memory content is necessary for showing, how the MESI protocol ensure the cache coherence when different write and read accesses happen to the same memory block. The content of the cache memories could not be changed. By loading the component the values of all cache blocks are set to null by default and they will be changed only by the system.

The files "memmesi.bin" and "processor.bin" in the RaVi directory include the default memory and processor content. These contents will be used by the multimedia component by default, but the user can interactively change the default content by specifying another external file or by editing the given content. This can be done by selecting the memory unit or a processor in the structure and using the right mouse menu item "edit". After the selection of the menu item "edit" a window is opened which shows the contents of the unit. Within this window the user can edit the contents or load another external file. Illustration 4 shows for example the edit window for the memory and processor contents.




Illustration 4: Edit Window for Memory and Processor Content



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January 2003 Prof. Dr. Peter Marwedel, Birgit Sirocic