Universität Dortmund Universität Dortmund
Department of Computer Science 12


Visualization of Computer Architecture (RaVi)

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Pipeline

Visualization Control | Edit Memory and Register File | Documentation "pipeline1" | Mips Instruction Set | Instruction and Data Memory Content | Register File Content | Component "pipeline2" | Component "pipeline3"

The following text explains the control and interaction of the component "pipeline1". Due to the fact that the control and interaction of the components "pipeline2" and "pipeline3" are identical to the one of component "pipeline1", the following description is valid also for the components "pipeline2" and "pipeline3". For further information about the content of the other components have a look to the documentation of "pipeline2" or documentation of "pipeline3".

By a clicking on one of the right icons you can start "pipeline1", "pipeline2" or "pipeline3" online. If everything works alright, an additional window will be opened with the loaded component and you can give it a try directly here.
If you prefer to test the components offline, you have to start the RaVi system on your computer first. After that you can load the component "pipeline1", "pipeline2" or "pipeline3". Loading the component means to open the subdesign file for example "pipeline1.hds" in the RaVi directory. For further information about installation and system start please have a look to the page Download - Loading a RaVi component

After a successfully loading of the component "pipeline1" you will see the schematic like the one shown in the illustraction 1 below. All signal lines are undefined. For a detail description of the hardware structure please have a look to the documentation page of this component.

Visualization Control

For starting the application flow of the component you have to click on the switch "clock". The switch "clock" represents a manual clock signal and every push on it corresponds to a single clock transition. The colors "grey" and "red" represent the signal values '0' and '1'. Every edge of the clock "clock" let the component goes on with the next step of the visualization.

 


Illustration 1: The Component "pipeline1"

The submenu and the hyperlinks give further information
During the visualization flow the instructions in the memory unit "IMem" are executed and passed through the different pipe stages. The active instructions are displayed in the table "Zyklus" under the schematic. Each column of the table represents the pipe stage which sit above it in the schematic. An instruction is shown in the column of the pipe stage in which it is situated.
Every instruction gets its own color and the relevant signal lines in the corresponding pipe stage are highlighted with this color. Illustration 2 shows the pipeline which contains the instruction "ADD" (black), "SUB" (yellow) and "AND" (grey). The red signal line at the input of the PC stands for the next instruction which will enter the pipe stage "Instruction Fetch".

Illustration 2: Visualizing the Instructions in the Different Pipe Stages. Visualization is shown after a falling edge of the clock.

New values are loaded into the pipeline registers at rising edges of the clock. The illustration 3 for example shows the datapath after a rising edge.

Illustration 3: Situation is shown after a Rising Edge of the Clock.

By moving the mouse over an element in the schematic the actual values of the input and output pins of the datapath elements can be seen. A popup window with the value will appear after a while.

Edit Memory and Register File

The files "mem.bin" and "reg.bin" in the RaVi directory contain the memory contents and the register file contents. These contents will be used by the multimedia component by default, but the user can interactively change the default content by specifying another external file or by editing the given contents. This can be done by selecting the memory unit or register file in the schematic and using the right mouse menu item "edit". After the selection of the menu item "edit" a window is opened which shows the contents of the unit. Within this window the user can edit the contents or load another external file. Illustration 3 shows for example the edit window for the memory and register file contents.



Illustration 3: Edit Window for Memory and Register File Content



To the Top | Visualization Control | Edit Memory and Register File | Documentation "pipeline1" | Mips Instruction Set | Instruction and Data Memory Content | Register File Content | Component "pipeline2" | Component "pipeline3"



January 2003 Prof. Dr. Peter Marwedel, Birgit Sirocic