Pipeline1
Differences Hennessy & Patterson |
Mips Instruction Set |
Instruction and Data Memory Content |
Register File Content |
Usage "pipeline1" |
Component "pipeline2" |
Component "pipeline3" |
Component "microprog"
The component "pipeline1" demonstrates, how pipelining
can be implemented by a hardware structure and visualizes how the instructions
pass through the different pipeline stages. The component simulates
the execution of instructions and shows the dynamic behaviour of the
pipelined datapath. It represents a simple pipeline without the dealing
of data hazards and branches.
For the visualization of pipelining we have also realized two additional
components. Component "pipeline2"
is an extention of component "pipeline1" and includes additionally the
handling of data hazards.
Component "pipeline3" is an
extention of component "pipeline2" and contains an additional
handling of branches.
The hardware structure specified
in this component is a pipelined implementation of the MIPS
(Mixed Instruction Processor Set).
The implementation is
widely identical to the one described in appendix A.3 of the book "Computer
Architecture, A Quantitative Approach (third edition)" from Hennessy &
Patterson. A schematic of the hardware structure is given in illustration 1.
For the visualization of an unpipelined implementation of the MIPS
see component "MicroProg".
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The submenu and the hyperlinks give further
information
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Illustration 1: Hardware Structure implemented in pipeline1.hds
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The schematic of the component "pipeline1" repesents
the hardware structure and at the same time it defines the appearance of
the visualization.
At the bottom of the component you find also the table "Zyklus".
Each column of the table represent a pipe stage. During the visualization
the active instructions will be displayed in the columns according to their
current pipe stage.
The schematic shows the
different pipe stages and the pipeline registers "IF/ID",
"ID/EX", "EX/MEM" and
"MEM/WB".
At the top line you can see five controllers, named "Control".
There is one controller given for each pipe stage and each of them controls the
execution of the corresponding pipe stage.
In the first pipe stage "Instruction Fetch"
you can find the program counter "PC",
the instruction memory unit "IMem",
and the ALU "+" for the address
calculation.
The pipe stage "Instruction Decode" contains
the register file "Reg" and the sign-extension unit "SE".
In the pipeline stage "Execution" you can see the arithmetic and logical
unit "ALU" and two multiplexers at the ALU inputs.
The pipe stage "Memory" includes only the data memory unit
"DMem" and
the pipe stage "Write Back" shows the multiplexer
which serves the result value according to the current instruction type.
The clock signal is given by the switch "clock" under the program counter.
With the switch "clock" the
user can control the application flow of the visualization.
The switch "clock" represents the manual clock cycle.
We have not integrated a self-controlled clock signal
because the clock cycles should be triggered by the user.
New values
are loaded into the pipeline registers at rising edges of the clock
with the exception of the program counter. The new values of the program counter
are loaded at falling edges of the clock.
The memory units and the register file serve their output values
at falling edges of the clock.
The light green lines represent the signals between the datapath elements.
If they are colored in light green, they are not relevant in
the actual cycle.
The relevant signals in a cycle will be highlighted with
different colors later during the visualization. Each active instruction
will get its own color and the signals will be colored
according to the instruction they belong to.
This is important and
quite different to the behaviour of a normal digital simulator system. A
conventional simulator highlights all signal lines according to their
values. Hence, for learning the basic pipeline concepts the conventional
visualization is not useful. With our accentuation method the user can easily
follow the way how the pipeline works.
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The content of the instruction memory unit (the
current MIPS instructions), the content of the data memory unit and
the content of the register file are not
determined by the component. The user can change them interactively during
the visualization. The instructions in the memory unit can be entered
either as assembler code or as 32bit strings. The data memory values
and the register values have to be entered as 32bit strings. The
default instruction and data memory content
and the default register file content are
given in the file "imem.bin", "dmem.bin" and "reg.bin" respectively.
These files are situated in the RaVi directory and
will be loaded automatically during the start of the component.
A detail description of the control and interaction facilities of this
component you will find on the page
Usage of this component.
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Differences to Hennessy & Patterson
First of all it is
important to mention that the hardware structure implemented in this
component only includes a
subset of the core MIPS instruction set.
With intent to develop a training component we have realised only a
selected subset in order to explain the execution of MIPS instructions. We
have not implemented a complete simulation model of the MIPS-processor.
We have implemented an additional multiplexer in the
pipe stage "Instruction Decode". The destination register field
is in one of two different places depending on the instruction type.
So we need a multiplexer to choose the correct portion of the IR in the
MEM/WB register to specify the register destination field.
The hardware structure described in the book
of Hennessy & Patterson does not take this into consideration.
The lack of a zero detection unit in the pipe stage "Execution"
is another difference to Hennessy & Patterson.
During the execution of a branche the ALU is used for the zero test
and for the jump address calculation. Consequently we will get a structure hazard
and the component "pipeline1" can not execute branches correctly.
Due to the fact that the component "pipeline3"
deals with branches, we have decided to ignore the structure hazard here
in this component. For further particulars of branches we refer you to
component "pipeline3".
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To the Top |
Differences Hennessy & Patterson |
Mips Instruction Set |
Instruction and Data Memory Content |
Register File Content |
Usage "pipeline1" |
Component "pipeline2" |
Component "pipeline3" |
Component "microprog"
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