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Department of Computer Science 12


 

Visualization of Computer Architecture (RaVi)

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Microprog

Differences Hennessy & Patterson | Misp Instruction Set | Memory Content | Register File Content | Usage "microprog"

The component "microprog" demonstrates, how the Mixed Instruction Set Processor (MISP) instruction set can be implemented by a hardware structure and visualises the dynamic behaviour of the datapath. The component simulates the execution of MISP instructions and shows the data transfers within the hardware structure.

The hardware structure specified in this component is a multicycle implementation of the MISP-processor. Implying that the hardware structure uses more than one clock cycle to complete the execution of a single instruction. The implementation is widely identical to the one described in chaper 5.4 of the book "Computer Organization and Design" from Hennessy & Patterson. A schematic of the hardware structure is given in illustration 1.
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Illustration 1: Hardware Structure implemeted in mircoprog.hds

The schematic of the component "microprog" repesents the hardware structure and at the same time it defines the appearance of the visualization. It shows the controller, the program counter "PC" with the write control gate "B", the memory unit "Mem", the instruction register "IR", the sign-extension unit "s.ex", the register file "Reg", the arithmetic and logical unit "ALU", the ALU control gate "Control", the ALU out register "T" and the gate "Concat" which has the task to build the jump address.
With the two switches "nreset" and "clock" the user can control the application flow of the visualization. The switch "nreset" enables the controller and the switch "clock" represents the manual clock cycle. We have not integrated a self-controlled clock signal because the clock cycles should be triggered by the user.

The thick light blue lines represent the control signals from the controller to the CPU. The thin light blue lines represent the signals between the datapath elements. If they are colored in light blue, they are not relevant in the actual cycle. The color "light blue" represent the logical value "undefined" in the Hades system.
The relevant signals in a cycle will be highlighted with different colors later during the visualization. This is important and quite different to the behaviour of a normal digital simulator system. A conventional simulator highlights all signal lines according to their values. Hence, for learning the basic concepts the conventional visualization is too complex and inconvenient.

The content of the memory unit, the current MISP instructions, and the content of the register file are not determined by the component. The user can change them interactively during the visualization. The instructions in the memory unit can be entered either as assembler code or as 32bit strings. The register values of the register file have to be entered as 32bit strings. The default memory content and the default register file content are given in the file "mem.bin" and "reg.bin" respectively. These files are situated in the RaVi directory and will be loaded automatically during the start of the component.

The finite state machine realised in this component takes only those states into account which are necessary for the selected MISP instructions of the component. This means that the implemented finite state machine specifies not a controller for the complete core MISP instruction set.

A detail description of the control and interaction facilities of this component you will find on the page Usage of this component.

Differences to Hennessy & Patterson

First of all it is important to mention that the hardware structure implemented in this component only includes a subset of the core MISP instruction set. With intent to develop a training component we have realised only a selected subset in order to explain the execution of MISP instructions. We have not implemented a complete simulation model of the MISP-processor.

For keeping the hardware structure as simple as possible we have avoided implementing the register LO and HI within our component. Consequently the instructions mult and div have a different instruction formation. The current format should include a explicit specification of a target register which finally contains the result of the operation. For having a look at a list of all instructions implemented in this component and the particular variations of the formats click here.

Because of the fact that our implementation should be able to execute the MISP instruction subset with opcode "00", the controller needs not only the opcode part (bit 31 to 26) of the instruction register but also the function part (bit 5 to 0) as input. This is different to the implementation of Hennessy & Patterson.

In the book of Hennessy & Patterson the jump address is computed by the function PC[31:28] || (IR[25:0]<<2). Because of the different interpretations of the shift function we have decided to concat simply PC[[31:28], IR[25:0] and a constant bit string of "00" to compute the jump address. This makes also a difference to the implementation of Hennessy & Patterson.



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January 2003 Prof. Dr. Peter Marwedel, Birgit Sirocic