# hades.models.Design file # [name] CacheProtocol [components] hades.models.InfoMessage i24 -3100 900 @N 1001 hades.models.RaViLogo i23 2850 20050 @N 1001 hades.models.cacheMESI.IpinDown i22 33000 1200 @N 1001 U hades.models.cacheMESI.IpinDown i21 30600 1200 @N 1001 U hades.models.cacheMESI.IpinDown i20 24600 1200 @N 1001 U hades.models.cacheMESI.Snoop i9 4200 10650 @N 1001 hades.models.cacheMESI.IpinDown i19 22200 1200 @N 1001 U hades.models.cacheMESI.Cache4MESI i8 28800 6600 @N 1001 4 16 hades.models.cacheMESI.IpinDown i18 16200 1200 @N 1001 U hades.models.cacheMESI.Cache3MESI i7 20400 6600 @N 1001 4 16 hades.models.cacheMESI.IpinDown i17 13800 1200 @N 1001 U hades.models.cacheMESI.Cache2MESI i6 12000 6600 @N 1001 4 16 hades.models.cacheMESI.IpinDown i16 7800 1200 @N 1001 U hades.models.cacheMESI.Cache1MESI i5 3600 6600 @N 1001 4 16 hades.models.cacheMESI.IpinDown i15 5400 1200 @N 1001 U hades.models.cacheMESI.CacheLineState i4 32400 16500 @N 1001 hades.models.cacheMESI.BusMESI i14 2400 13950 @N 1001 hades.models.cacheMESI.Processor i3 28800 2400 @N 1001 32 16 processor.bin hades.models.cacheMESI.Snoop i13 29400 10650 @N 1001 hades.models.cacheMESI.Processor i2 20400 2400 @N 1001 32 16 processor.bin hades.models.cacheMESI.Snoop i12 21000 10650 @N 1001 hades.models.cacheMESI.Processor i1 12000 2400 @N 1001 32 16 processor.bin hades.models.cacheMESI.Processor i0 3600 2400 @N 1001 32 16 processor.bin hades.models.cacheMESI.Snoop i11 12600 10650 @N 1001 hades.models.cacheMESI.MemMESI i10 18600 16200 @N 1001 32 16 memmesi.bin hades.models.io.Step i25 19200 1800 @N 1001 U hades.models.cacheMESI.InfoMESI i24 3000 17000 @N 1001 [end components] [signals] hades.signals.SignalStdLogic1164 n39 11 i25 Y i1 step i0 step i6 step i2 step i7 step i3 step i8 step i14 step i10 step i5 step 37 2 19200 1800 19200 3600 2 19200 3600 18600 3600 2 19200 1800 19200 5400 2 19200 5400 10800 5400 2 10800 5400 10800 3600 2 10800 3600 10200 3600 2 19200 1800 19200 5400 2 19200 5400 18600 5400 2 18600 5400 18600 6600 2 19200 1800 19200 5400 2 19200 5400 27600 5400 2 27600 5400 27600 3600 2 27600 3600 27000 3600 2 19200 1800 19200 5400 2 19200 5400 27000 5400 2 27000 5400 27000 6600 2 19200 1800 19200 5400 2 19200 5400 36000 5400 2 36000 5400 36000 3600 2 36000 3600 35400 3600 2 19200 1800 19200 5400 2 19200 5400 35400 5400 2 35400 5400 35400 6600 2 19200 1800 19200 5400 2 19200 5400 36000 5400 2 36000 5400 37200 5400 2 37200 5400 37200 14550 2 37200 14550 36000 14550 2 19200 1800 19200 5400 2 19200 5400 37200 5400 2 37200 5400 37200 15600 2 37200 15600 30000 15600 2 30000 15600 30000 16200 2 10200 3600 10800 3600 2 10800 3600 10800 5400 2 10800 5400 10200 5400 2 10200 5400 10200 6600 7 10200 3600 19200 5400 10800 5400 37200 5400 10800 3600 19200 1800 36000 5400 hades.signals.SignalStdLogicVectorRaVi n38 16 2 i10 dataOut i14 memDataIn 1 2 26400 16200 26400 15150 0 hades.signals.SignalStdLogic1164 n37 2 i14 rwMem i10 readWrite 1 2 25200 15150 25200 16200 0 hades.signals.SignalStdLogicVectorRaVi n36 16 2 i14 memDataOut i10 dataIn 1 2 24000 15150 24000 16200 0 hades.signals.SignalStdLogicVectorRaVi n35 5 2 i8 signalOut i14 signalIn4 1 2 34200 9000 34200 13950 0 hades.signals.SignalStdLogicVectorRaVi n34 16 2 i8 busDataOut i14 cacheDataIn4 1 2 31200 9000 31200 13950 0 hades.signals.SignalStdLogicVectorRaVi n33 16 2 i8 procDataOut i3 dataIn 1 2 33600 6600 33600 4800 0 hades.signals.SignalStdLogicVectorRaVi n32 16 2 i3 dataOut i8 procDataIn 1 2 32400 4800 32400 6600 0 hades.signals.SignalStdLogic1164 n31 2 i3 cacheReadWrite i8 readWrite 1 2 31200 4800 31200 6600 0 hades.signals.SignalStdLogicVectorRaVi n30 5 3 i3 address i8 address i14 addressIn4 4 2 28800 4200 28200 4200 2 28200 4200 28200 7950 2 28200 7950 28800 7950 2 28200 7950 28200 13950 1 28200 7950 hades.signals.SignalStdLogic1164 n29 2 i22 Y i3 write 1 2 33000 1200 33000 2400 0 hades.signals.SignalStdLogic1164 n28 2 i21 Y i3 read 1 2 30600 1200 30600 2400 0 hades.signals.SignalStdLogicVectorRaVi n27 5 2 i7 signalOut i14 signalIn3 1 2 25800 9000 25800 13950 0 hades.signals.SignalStdLogicVectorRaVi n26 16 2 i7 busDataOut i14 cacheDataIn3 1 2 22800 9000 22800 13950 0 hades.signals.SignalStdLogicVectorRaVi n25 16 2 i7 procDataOut i2 dataIn 1 2 25200 6600 25200 4800 0 hades.signals.SignalStdLogicVectorRaVi n24 16 2 i2 dataOut i7 procDataIn 1 2 24000 4800 24000 6600 0 hades.signals.SignalStdLogic1164 n23 2 i2 cacheReadWrite i7 readWrite 1 2 22800 4800 22800 6600 0 hades.signals.SignalStdLogicVectorRaVi n22 5 3 i2 address i7 address i14 addressIn3 4 2 20400 4200 19800 4200 2 19800 4200 19800 7950 2 19800 7950 20400 7950 2 19800 7950 19800 13950 1 19800 7950 hades.signals.SignalStdLogic1164 n21 2 i20 Y i2 write 1 2 24600 1200 24600 2400 0 hades.signals.SignalStdLogic1164 n20 2 i19 Y i2 read 1 2 22200 1200 22200 2400 0 hades.signals.SignalStdLogicVectorRaVi n9 16 2 i5 procDataOut i0 dataIn 1 2 8400 6600 8400 4800 0 hades.signals.SignalStdLogicVectorRaVi n8 16 2 i0 dataOut i5 procDataIn 1 2 7200 4800 7200 6600 0 hades.signals.SignalStdLogic1164 n7 2 i0 cacheReadWrite i5 readWrite 1 2 6000 4800 6000 6600 0 hades.signals.SignalStdLogic1164 n6 2 i16 Y i0 write 1 2 7800 1200 7800 2400 0 hades.signals.SignalStdLogic1164 n5 2 i15 Y i0 read 1 2 5400 1200 5400 2400 0 hades.signals.SignalStdLogicVectorRaVi n4 5 3 i0 address i5 address i14 addressIn1 4 2 3600 4200 3000 4200 2 3000 4200 3000 7950 2 3000 7950 3600 7950 2 3000 7950 3000 13950 1 3000 7950 hades.signals.SignalStdLogicVectorRaVi n3 5 2 i13 out i8 snoop 1 2 30000 9000 30000 10650 0 hades.signals.SignalStdLogicVectorRaVi n2 5 2 i12 out i7 snoop 1 2 21600 9000 21600 10650 0 hades.signals.SignalStdLogicVectorRaVi n1 5 2 i11 out i6 snoop 1 2 13200 9000 13200 10650 0 hades.signals.SignalStdLogicVectorRaVi n0 5 2 i9 out i5 snoop 1 2 4800 9000 4800 10650 0 hades.signals.SignalStdLogicVectorRaVi n19 5 2 i6 signalOut i14 signalIn2 1 2 17400 9000 17400 13950 0 hades.signals.SignalStdLogicVectorRaVi n18 16 2 i6 busDataOut i14 cacheDataIn2 1 2 14400 9000 14400 13950 0 hades.signals.SignalStdLogicVectorRaVi n17 16 2 i6 procDataOut i1 dataIn 1 2 16800 6600 16800 4800 0 hades.signals.SignalStdLogicVectorRaVi n16 16 2 i1 dataOut i6 procDataIn 1 2 15600 4800 15600 6600 0 hades.signals.SignalStdLogic1164 n15 2 i1 cacheReadWrite i6 readWrite 1 2 14400 4800 14400 6600 0 hades.signals.SignalStdLogicVectorRaVi n14 5 3 i1 address i6 address i14 addressIn2 5 2 12000 4200 11400 4200 2 11400 4200 11400 8100 2 11400 8100 12000 8100 2 12000 8100 12000 7950 2 11400 8100 11400 13950 1 11400 8100 hades.signals.SignalStdLogic1164 n13 2 i18 Y i1 write 1 2 16200 1200 16200 2400 0 hades.signals.SignalStdLogic1164 n12 2 i17 Y i1 read 1 2 13800 1200 13800 2400 0 hades.signals.SignalStdLogicVectorRaVi n11 5 2 i5 signalOut i14 signalIn1 1 2 9000 9000 9000 13950 0 hades.signals.SignalStdLogicVectorRaVi n43 4 5 i14 block i8 block i7 block i6 block i5 block 20 2 35400 13950 35400 13350 2 35400 13350 36600 13350 2 36600 13350 36600 6000 2 36600 6000 34800 6000 2 34800 6000 34800 6600 2 35400 13950 35400 13350 2 35400 13350 36600 13350 2 36600 13350 36600 6000 2 36600 6000 26400 6000 2 26400 6000 26400 6600 2 35400 13950 35400 13350 2 35400 13350 36600 13350 2 36600 13350 36600 6000 2 36600 6000 18000 6000 2 18000 6000 18000 6600 2 35400 13950 35400 13350 2 35400 13350 36600 13350 2 36600 13350 36600 6000 2 36600 6000 9600 6000 2 9600 6000 9600 6600 4 36600 6000 36600 13350 35400 13950 35400 13350 hades.signals.SignalStdLogicVectorRaVi n42 5 6 i14 addressOut i10 address i13 in i12 in i11 in i9 in 22 2 18000 15150 18000 18900 2 18000 18900 18600 18900 2 18000 15150 18000 15900 2 18000 15900 1800 15900 2 1800 15900 1800 13500 2 1800 13500 30000 13500 2 30000 13500 30000 11850 2 18000 15150 18000 15900 2 18000 15900 1800 15900 2 1800 15900 1800 13500 2 1800 13500 21600 13500 2 21600 13500 21600 11850 2 18000 15150 18000 15900 2 18000 15900 1800 15900 2 1800 15900 1800 13500 2 1800 13500 13200 13500 2 13200 13500 13200 11850 2 18000 15150 18000 15900 2 18000 15900 1800 15900 2 1800 15900 1800 13500 2 1800 13500 4800 13500 2 4800 13500 4800 11850 4 18000 15150 1800 15900 1800 13500 18000 15900 hades.signals.SignalStdLogicVectorRaVi n10 16 2 i5 busDataOut i14 cacheDataIn1 1 2 6000 9000 6000 13950 0 hades.signals.SignalStdLogicVectorRaVi n41 5 5 i14 signalOut i8 signalIn i7 signalIn i6 signalIn i5 signalIn 10 2 18600 13950 18600 13050 2 18600 13050 35400 13050 2 35400 13050 35400 9000 2 18600 13950 18600 13050 2 18600 13050 27000 13050 2 27000 13050 27000 9000 2 18600 13950 18600 9000 2 18600 13950 18600 13050 2 18600 13050 10200 13050 2 10200 13050 10200 9000 2 18600 13050 18600 13950 hades.signals.SignalStdLogicVectorRaVi n40 16 5 i14 cacheDataOut i6 busDataIn i8 busDataIn i7 busDataIn i5 busDataIn 10 2 15600 13950 15600 9000 2 15600 13950 15600 12450 2 15600 12450 32400 12450 2 32400 12450 32400 9000 2 15600 13950 15600 12450 2 15600 12450 24000 12450 2 24000 12450 24000 9000 2 15600 13950 15600 12450 2 15600 12450 7200 12450 2 7200 12450 7200 9000 2 15600 13950 15600 12450 [end signals] [end]