# hades.models.Design file # [name] Microprogrammierung [components] hades.models.InfoStart i22 -900 17700 @N 1001 hades.models.InfoMessage i21 -2400 -600 @N 1001 hades.models.microProg.Or2MicroProg i20 2400 6000 @N 1001 1.0E-8 hades.models.microProg.T i9 32400 10200 @N 1001 32 UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU_B 1.0E-8 hades.models.microProg.ResetControl i19 6600 -600 @N 1001 U hades.models.microProg.Reg Reg 21000 9000 @N 1001 32 32 reg.bin hades.models.microProg.Alu i8 28200 8400 @N 1001 hades.models.RaViLogo i18 1500 22200 @N 1001 hades.models.microProg.Mux41MicroProg i7 25800 11400 @N 1001 hades.models.Takt i17 9300 17400 @N 1001 U hades.models.microProg.Mux21MicroProg i6 25800 7800 @N 1001 hades.models.microProg.StringDisplayRaVi i16 34800 4200 @N 1001 hades.models.microProg.Mux21_5 i5 18600 11400 @N 1001 hades.models.microProg.Mux21_U i15 17400 16200 @N 1001 hades.models.microProg.IR i4 13800 7800 @N 1001 32 10001100010000110000000001010000_B 1.0E-8 hades.models.microProg.Mux21MicroProg i3 6000 9000 @N 1001 hades.models.microProg.Mem Mem 8400 9600 @N 1001 32 32 mem.bin hades.models.microProg.SignExtend i14 18600 15000 @N 1001 hades.models.microProg.PC i2 3600 8400 @N 1001 32 00000000000000000000000000000100_B 1.0E-8 hades.models.microProg.AluControl i13 28800 15600 @N 1001 hades.models.microProg.ShiftLeftMicroProg i12 22200 15000 @N 1001 hades.models.microProg.And2MicroProg i1 4200 4200 @N 1001 1.0E-8 hades.models.microProg.Steuerwerk i0 2400 -1200 @N 1001 /hades/models/microProg/steuerwerk.fsm hades.models.microProg.Concat i11 36000 12600 @N 1001 hades.models.microProg.Mux31MicroProg i10 37800 6600 @N 1001 [end components] [signals] hades.signals.SignalStdLogicVectorRaVi n39 32 2 i10 Y i2 D 4 2 38400 8400 39000 8400 2 39000 8400 39000 22200 2 39000 22200 4200 22200 2 4200 22200 4200 10800 0 hades.signals.SignalStdLogicVectorRaVi n38 4 2 i2 31:28 i11 I1 4 2 3600 10200 3000 10200 2 3000 10200 3000 21600 2 3000 21600 36600 21600 2 36600 21600 36600 14400 0 hades.signals.SignalStdLogicVectorRaVi n37 26 2 i4 25:0 i11 I2 3 2 14400 15000 14400 21000 2 14400 21000 37200 21000 2 37200 21000 37200 14400 0 hades.signals.SignalStdLogicVectorRaVi n36 32 2 i11 O i10 2 2 2 37200 12600 37200 9600 2 37200 9600 37800 9600 0 hades.signals.SignalStdLogic1164RaVi n35 2 i0 PCSource i10 cntrl 2 2 39000 3000 39000 6600 2 39000 6600 38400 6600 0 hades.signals.SignalStdLogicVectorRaVi n34 32 5 i9 Q i10 1 i3 1 Mem a2 i15 0 19 2 33600 11400 34200 11400 2 34200 11400 34200 8400 2 34200 8400 37800 8400 2 33600 11400 34200 11400 2 34200 11400 34200 20400 2 34200 20400 5400 20400 2 5400 20400 5400 10800 2 5400 10800 6000 10800 2 33600 11400 34200 11400 2 34200 11400 34200 20400 2 34200 20400 5400 20400 2 5400 20400 5400 12000 2 5400 12000 7800 12000 2 7800 12000 8400 11400 2 33600 11400 34200 11400 2 34200 11400 34200 20400 2 34200 20400 16200 20400 2 16200 20400 16200 18000 2 16200 18000 17400 18000 4 34200 20400 33600 11400 5400 20400 34200 11400 hades.signals.SignalStdLogicVectorRaVi n33 32 3 i8 OUT i10 0 i9 D 4 2 30600 11400 31800 11400 2 31800 11400 31800 7200 2 31800 7200 37800 7200 2 30600 11400 32400 11400 1 30600 11400 hades.signals.SignalStdLogicVectorRaVi n32 11 2 i4 10:0 i13 IR 4 2 16200 14400 16800 14400 2 16800 14400 16800 19800 2 16800 19800 30000 19800 2 30000 19800 30000 17400 0 hades.signals.SignalStdLogicVectorRaVi n31 32 2 i12 Y i7 3 1 2 24600 15600 25800 15600 0 hades.signals.SignalStdLogicVectorRaVi n30 32 3 i14 O i12 A i7 2 4 2 20400 15600 22200 15600 2 20400 15600 21600 15600 2 21600 15600 21600 14400 2 21600 14400 25800 14400 1 20400 15600 hades.signals.SignalStdLogic1164 n29 2 i0 RegWrite Reg RegWrite 1 2 22800 3000 22800 9000 0 hades.signals.SignalStdLogic1164 n28 2 i0 TargetWrite i9 TargetWrite 1 2 33000 3000 33000 10200 0 hades.signals.SignalStdLogicVectorRaVi n27 5 2 i0 ALUOp i13 ALUOp 3 2 31200 3000 31200 14400 2 31200 14400 30600 14400 2 30600 14400 30600 15600 0 hades.signals.SignalStdLogicVectorRaVi n26 32 2 i7 Y i8 OP2 3 2 26400 13800 27600 13800 2 27600 13800 27600 13200 2 27600 13200 28200 13200 0 hades.signals.SignalStdLogic1164RaVi n25 2 i0 ALUSelA i6 cntrl 1 2 26400 3000 26400 7800 0 hades.signals.SignalStdLogicVectorRaVi n24 32 3 Reg o2 i7 0 Mem i2 6 2 24000 12000 25800 12000 2 24000 12000 25200 12000 2 25200 12000 25200 19200 2 25200 19200 7800 19200 2 7800 19200 7800 13800 2 7800 13800 9000 13800 1 24000 12000 hades.signals.SignalStdLogicVectorRaVi n23 32 3 i2 Q i3 0 i6 0 6 2 4800 9600 6000 9600 2 4800 9600 5400 9600 2 5400 9600 5400 7200 2 5400 7200 25200 7200 2 25200 7200 25200 8400 2 25200 8400 25800 8400 1 4800 9600 hades.signals.SignalStdLogic1164RaVi n22 2 i0 ALUSelB i7 cntrl 2 2 27000 3000 27000 11400 2 27000 11400 26400 11400 0 hades.signals.SignalStdLogicVectorRaVi n21 16 2 i4 15:0 i14 I 2 2 15600 15000 15600 15600 2 15600 15600 18600 15600 0 hades.signals.SignalStdLogicVectorRaVi n20 32 2 i3 Y Mem a1 1 2 6600 10200 8400 10200 0 hades.signals.SignalStdLogicVectorRaVi n9 6 2 i4 5:0 i0 Funct 2 2 13800 8400 12600 8400 2 12600 8400 12600 3000 0 hades.signals.SignalStdLogicVectorRaVi n8 32 3 Mem o1 i4 D i15 1 4 2 11400 12000 13800 12000 2 11400 12000 12600 12000 2 12600 12000 12600 16800 2 12600 16800 17400 16800 1 11400 12000 hades.signals.SignalStdLogic1164 n7 2 i0 MemRead Mem MemRead 1 2 10800 3000 10800 9600 0 hades.signals.SignalStdLogic1164 n6 2 i0 MemWrite Mem MemWrite 1 2 9600 3000 9600 9600 0 hades.signals.SignalStdLogic1164RaVi n5 2 i0 IorD i3 cntrl 1 2 6600 3000 6600 9000 0 hades.signals.SignalStdLogic1164 n4 2 i8 Z i1 zero 3 2 29400 9000 29400 3600 2 29400 3600 5400 3600 2 5400 3600 5400 4200 0 hades.signals.SignalStdLogic1164 n3 2 i0 PCWriteC i1 PCWriteC 1 2 4800 3000 4800 4200 0 hades.signals.SignalStdLogic1164 n2 2 i1 Y i20 B 2 2 4800 5400 3600 5400 2 3600 5400 3600 6000 0 hades.signals.SignalStdLogic1164 n1 2 i20 Y i2 PCWrite 2 2 3600 7200 4200 7200 2 4200 7200 4200 8400 0 hades.signals.SignalStdLogic1164 n0 2 i0 PCWrite i20 PCWrite 1 2 3000 3000 3000 6000 0 hades.signals.SignalStdLogicVectorRaVi n19 32 2 Reg o1 i6 1 1 2 24000 9600 25800 9600 0 hades.signals.SignalStdLogicVectorRaVi n18 32 2 i6 Y i8 OP1 3 2 26400 9000 27600 9000 2 27600 9000 27600 9600 2 27600 9600 28200 9600 0 hades.signals.SignalStdLogicVectorRaVi n17 5 2 i5 Y Reg a3 3 2 19200 12600 19800 12600 2 19800 12600 19800 12000 2 19800 12000 21000 12000 0 hades.signals.SignalStdLogicVectorRaVi n16 6 2 i13 OUT i8 CNTRL 1 2 29400 15600 29400 13800 0 hades.signals.SignalStdLogicVectorRaVi n15 5 2 i4 15:11 i5 1 1 2 16200 13200 18600 13200 0 hades.signals.SignalStdLogicVectorRaVi n14 32 2 i15 Y Reg i3 3 2 18000 17400 21000 17400 2 21000 17400 21000 13200 2 21000 13200 21600 13200 0 hades.signals.SignalStdLogicVectorRaVi n13 5 3 i4 20:16 Reg a2 i5 0 4 2 16200 10800 21000 10800 2 16200 10800 17400 10800 2 17400 10800 17400 12000 2 17400 12000 18600 12000 1 16200 10800 hades.signals.SignalStdLogicVectorRaVi n12 5 2 i4 25:21 Reg a1 1 2 16200 9600 21000 9600 0 hades.signals.SignalStdLogic1164 n44 7 i17 Y Mem clk i9 CLK i4 CLK Reg CS i2 CLK i0 clk 16 2 9300 17400 10200 17400 2 10200 15600 10200 14400 2 10200 17400 10200 22800 2 21300 22800 33000 22800 2 33000 22800 33000 12600 2 10200 22800 15000 22800 2 15000 22800 15000 15000 2 15000 22800 21300 22800 2 21300 22800 21300 15000 2 21300 15000 22800 13800 2 10200 17400 10200 15600 2 10200 15600 1800 15600 2 1800 15600 1800 9600 2 1800 9600 3600 9600 2 1800 9600 1800 0 2 1800 0 2400 0 5 10200 15600 10200 17400 15000 22800 21300 22800 1800 9600 hades.signals.SignalStdLogic1164 n11 2 i0 IRWrite i4 IRWrite 1 2 15000 3000 15000 7800 0 hades.signals.SignalStdLogic1164 n43 3 i19 Y i0 nreset i2 RESET 6 2 6000 -600 2400 -600 2 6600 -600 6000 -600 2 6000 -600 6000 -900 2 6000 -900 2100 -900 2 2100 -900 2100 9000 2 2100 9000 3600 9000 1 6000 -600 hades.signals.SignalStdLogicVectorRaVi n10 6 2 i4 31:26 i0 OpCode 2 2 16200 8400 16800 8400 2 16800 8400 16800 3000 0 hades.signals.SignalStdLogic1164RaVi n42 2 i0 MemToReg i15 cntrl 1 2 18000 3000 18000 16200 0 hades.models.string.StringSignal n41 2 i0 state i16 A 3 2 39600 0 40200 0 2 40200 0 40200 4800 2 40200 4800 38400 4800 0 hades.signals.SignalStdLogic1164RaVi n40 2 i0 RegDest i5 cntrl 1 2 19200 3000 19200 11400 0 [end signals] [end]