# hades.models.Design file # [name] Scoreboard [components] hades.models.scoreboard.PCScoreboard i8 2700 10500 @N 1001 hades.models.scoreboard.MemScoreboard i7 6600 2400 @N 1001 32 32 memscoreboard.bin hades.models.scoreboard.RegScoreboard i6 13200 2400 @N 1001 64 32 regscoreboard.bin hades.models.scoreboard.DivideUnit i5 31200 4500 @N 1001 hades.models.scoreboard.MultUnit i4 25200 4500 @N 1001 hades.models.scoreboard.AddUnit i3 19200 4500 @N 1001 hades.models.scoreboard.IntegerUnit i2 13200 4500 @N 1001 hades.models.scoreboard.Scoreboard i1 12600 9300 @N 1001 hades.models.scoreboard.InstrStream i0 4500 8100 @N 1001 24 32 instrstream.bin hades.models.InfoMessage i12 38000 11600 @N 1001 hades.models.InfoStart i11 27300 -200 @N 1001 hades.models.RaViLogo i10 3300 0 @N 1001 hades.models.Takt i9 24000 600 @N 1001 U [end components] [signals] hades.signals.SignalStdLogic1164RaVi n27_0_1 7 i9 Y i6 clock i5 clock i4 clock i3 clock i2 clock i1 step 20 2 24000 1800 24000 2400 2 24000 1800 36600 1800 2 36600 1800 36600 5700 2 36600 5700 34200 5700 2 24000 1800 36600 1800 2 36600 1800 36600 6900 2 36600 6900 28200 6900 2 28200 6900 28200 5700 2 24000 1800 36600 1800 2 36600 1800 36600 6900 2 36600 6900 22200 6900 2 22200 6900 22200 5700 2 24000 1800 36600 1800 2 36600 1800 36600 6900 2 36600 6900 16200 6900 2 16200 6900 16200 5700 2 24000 1800 24000 600 2 24000 1800 12000 1800 2 12000 1800 12000 9300 2 12000 9300 12600 9300 3 36600 1800 24000 1800 36600 6900 hades.signals.SignalStdLogicVectorRaVi n9 32 2 i6 addOp1 i3 OP1 1 2 19800 4500 19800 3600 0 hades.signals.SignalStdLogicVectorRaVi n8 32 4 i2 OUT i6 intResult i7 a i8 addressIn 10 2 15000 6300 15000 7050 2 15000 7050 17400 7050 2 17400 7050 17400 3600 2 15000 6300 15000 7050 2 15000 7050 11400 7050 2 11400 7050 11400 5400 2 11400 5400 10650 5400 2 15000 6300 15000 7050 2 15000 7050 3300 7050 2 3300 7050 3300 10500 2 15000 6300 15000 7050 hades.signals.SignalStdLogicVectorRaVi n7 8 2 i2 status i1 intUnitStatus 1 2 15600 6300 15600 8100 0 hades.signals.SignalStdLogicVectorRaVi n6 32 2 i1 cntrIntUnit i2 cntr 1 2 14400 6300 14400 8100 0 hades.signals.SignalStdLogicVectorRaVi n5 32 2 i6 intOp2 i2 OP2 1 2 16200 3600 16200 4500 0 hades.signals.SignalStdLogicVectorRaVi n19 32 2 i6 divOp1 i5 OP1 1 2 31800 4500 31800 3600 0 hades.signals.SignalStdLogicVectorRaVi n4 32 2 i6 intOp1 i2 OP1 1 2 13800 4500 13800 3600 0 hades.signals.SignalStdLogicVectorRaVi n18 32 2 i4 OUT i6 multResult 3 2 27000 6300 27000 7200 2 27000 7200 29400 7200 2 29400 7200 29400 3600 0 hades.signals.SignalStdLogicVectorRaVi n3 32 2 i7 o i6 memIn 1 2 10050 2550 13200 2550 0 hades.signals.SignalStdLogicVectorRaVi n17 8 2 i4 status i1 multUnitStatus 1 2 27600 6300 27600 8100 0 hades.signals.SignalStdLogicVectorRaVi n2 32 2 i5 OUT i6 divResult 4 2 33000 6300 33000 7200 2 33000 7200 35400 7200 2 35400 7200 35400 3000 2 35400 3000 34800 3000 0 hades.signals.SignalStdLogicVectorRaVi n16 6 2 i1 cntrMultUnit i4 cntr 1 2 26400 6300 26400 8100 0 hades.signals.SignalStdLogicVectorRaVi n1 32 2 i0 instr i1 instrIn 1 2 11400 11700 12600 11700 0 hades.signals.SignalStdLogicVectorRaVi n15 32 2 i6 multOp2 i4 OP2 1 2 28200 4500 28200 3600 0 hades.signals.SignalStdLogicVectorRaVi n0 32 2 i8 addressOut i0 addressIn 1 2 3900 11700 4500 11700 0 hades.signals.SignalStdLogicVectorRaVi n14 32 2 i6 multOp1 i4 OP1 1 2 25800 4500 25800 3600 0 hades.signals.SignalStdLogicVectorRaVi n13 32 2 i3 OUT i6 addResult 3 2 21000 6300 21000 7200 2 21000 7200 23400 7200 2 23400 7200 23400 3600 0 hades.signals.SignalStdLogicVectorRaVi n12 8 2 i3 status i1 addUnitStatus 1 2 21600 6300 21600 8100 0 hades.signals.SignalStdLogicVectorRaVi n11 6 2 i1 cntrAddUnit i3 cntr 1 2 20400 6300 20400 8100 0 hades.signals.SignalStdLogicVectorRaVi n10 32 2 i6 addOp2 i3 OP2 1 2 22200 4500 22200 3600 0 hades.signals.SignalStdLogic1164 n28 2 i1 pcWrite i8 readWrite 3 2 23400 25050 23400 25350 2 23400 25350 4200 25350 2 4200 25350 3300 12900 0 hades.signals.SignalStdLogicVectorRaVi n27 32 2 i7 d i6 memOut 1 2 10050 3150 13200 3150 0 hades.signals.SignalStdLogicVectorRaVi n26 15 2 i1 cntr3 i6 cntr3 1 2 30000 3600 30000 8100 0 hades.signals.SignalStdLogicVectorRaVi n25 15 2 i1 cntr2 i6 cntr2 1 2 24000 3600 24000 8100 0 hades.signals.SignalStdLogicVectorRaVi n24 15 2 i1 cntr1 i6 cntr1 1 2 18000 3600 18000 8100 0 hades.signals.SignalStdLogicVectorRaVi n23 15 2 i1 cntr4 i6 cntr4 4 2 34800 2700 36000 2700 2 36000 2700 36000 7500 2 36000 7500 34200 7500 2 34200 7500 34200 8100 0 hades.signals.SignalStdLogicVectorRaVi n22 8 2 i5 status i1 divUnitStatus 1 2 33600 6300 33600 8100 0 hades.signals.SignalStdLogicVectorRaVi n21 6 2 i1 cntrDivUnit i5 cntr 1 2 32400 6300 32400 8100 0 hades.signals.SignalStdLogicVectorRaVi n20 32 2 i6 divOp2 i5 OP2 1 2 34200 4500 34200 3600 0 [end signals] [end]