| Mikail Yayla.
Resource-Aware Acceleration for Nano Particle Classification.
Master's Thesis, 2019
[BibTeX][PDF]@mastersthesis { 2019-yayla,
title = {Resource-Aware Acceleration for Nano Particle Classification},
author = {Yayla, Mikail},
school = {TU Dortmund},
year = {2019},
file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/2019-yayla.pdf},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen and Dr. Kuan-Hsun Chen},
} |
| Christian Hakert, Kuan-Hsun Chen, Mikail Yayla, Georg von der Brüggen, Sebastian Bloemeke and Jian-Jia Chen.
Software-Based Memory Analysis Environments for In-Memory Wear-Leveling.
In 25th Asia and South Pacific Design Automation Conference ASP-DAC 2020, Invited Paper
Beijing, China, 2019
[BibTeX][Abstract]@inproceedings { nvmsimulator,
author = {Hakert, Christian and Chen, Kuan-Hsun and Yayla, Mikail and Br\"uggen, Georg von der and Bloemeke, Sebastian and Chen, Jian-Jia},
title = {Software-Based Memory Analysis Environments for In-Memory Wear-Leveling},
booktitle = {25th Asia and South Pacific Design Automation Conference ASP-DAC 2020, Invited Paper},
year = {2019},
address = {Beijing, China},
keywords = {kuan, nvm-oma, georg},
confidential = {n},
abstract = {Emerging non-volatile memory (NVM) architectures are considered as a replacement for DRAM and storage in the near future, since NVMs provide low power consumption, fast access speed, and low unit cost. Due to the lower write-endurance of NVMs, several in-memory wear-leveling techniques have been studied over the last years. Since most approaches propose or rely on specialized hardware, the techniques are often evaluated based on assumptions and in-house simulations rather than on real systems. To address this issue, we develop a setup consisting of a gem5 instance and an NVMain2.0 instance, which simulates an entire system (CPU, peripherals, etc.) together with an NVM plugged into the system. Taking a recorded memory access pattern from a low-level simulation into consideration to design and optimize wear-leveling techniques as operating system services allows a cross-layer design of wear- leveling techniques. With the insights gathered by analyzing the recorded memory access patterns, we develop a software-only wear-leveling solution, which does not require special hardware at all. This algorithm is evaluated afterwards by the full system simulation.},
}
Emerging non-volatile memory (NVM) architectures are considered as a replacement for DRAM and storage in the near future, since NVMs provide low power consumption, fast access speed, and low unit cost. Due to the lower write-endurance of NVMs, several in-memory wear-leveling techniques have been studied over the last years. Since most approaches propose or rely on specialized hardware, the techniques are often evaluated based on assumptions and in-house simulations rather than on real systems. To address this issue, we develop a setup consisting of a gem5 instance and an NVMain2.0 instance, which simulates an entire system (CPU, peripherals, etc.) together with an NVM plugged into the system. Taking a recorded memory access pattern from a low-level simulation into consideration to design and optimize wear-leveling techniques as operating system services allows a cross-layer design of wear- leveling techniques. With the insights gathered by analyzing the recorded memory access patterns, we develop a software-only wear-leveling solution, which does not require special hardware at all. This algorithm is evaluated afterwards by the full system simulation.
|
| Christian Hakert, Mikail Yayla, Kuan-Hsun Chen, Georg von der Brüggen, Jian-Jia Chen, Sebastian Buschjäger, Katharina Morik, Paul R. Genssler, Lars Bauer, Hussam Amrouch and Jörg Henkel.
Stack Usage Analysis for Efficient Wear Leveling in Non-Volatile Main Memory Systems.
In 1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)
Alberta, Canada, 2019
[BibTeX][Abstract]@inproceedings { mlcad2019stackanalysis,
author = {Hakert, Christian and Yayla, Mikail and Chen, Kuan-Hsun and Br\"uggen, Georg von der and Chen, Jian-Jia and Buschj\"ager, Sebastian and Morik, Katharina and Genssler, Paul R. and Bauer, Lars and Amrouch, Hussam and Henkel, J\"org},
title = {Stack Usage Analysis for Efficient Wear Leveling in Non-Volatile Main Memory Systems},
booktitle = {1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD) },
year = {2019},
address = {Alberta, Canada},
keywords = {kuan, nvm-oma, georg},
confidential = {n},
abstract = {Emerging non-volatile memory (NVM) technologies, such as Phase Change Memory (PCM), have been considered as a replacement for DRAM and storage due to their low power consumption, fast access speed, and low unit cost. Even so, some NVMs have a significantly lower write endurance and hence in-memory wear leveling is an important requirement for practical applicability. Since writes to the stack often target a small and dense memory region, generic, coarse-grained wear-leveling mechanisms (e.g. virtual memory page remapping) are not sufficient. An alternative solution is to relocate the stack memory regularly, which involves copying of the stack content. As the stack content changes in size during the execution of an application, the copy overhead can be significantly mitigated by performing the relocation when the stack size is small. In this paper, we investigate two approaches to determine points in time when the stack is small. First, we analyze the possibility to fit simple machine-learning models to the stack usage function. Precise predictions of this function enable the identification of the minimum stack size during execution. In our evaluation, the tested models provide accurate estimates of the future stack usage function for a subset of common applications. As a second approach, we analyze applications a priori and determine potential optimal points to perform relocation in the instruction stream. In detail, we deploy the application in an analysis environment, which determines a rating for each executed instruction. Based on this rating, we apply a genetic algorithm to identify the best points in the instruction stream to perform the stack relocation. This approach allows to save up to 85% of the write overhead for wear-leveling in our experiments.},
}
Emerging non-volatile memory (NVM) technologies, such as Phase Change Memory (PCM), have been considered as a replacement for DRAM and storage due to their low power consumption, fast access speed, and low unit cost. Even so, some NVMs have a significantly lower write endurance and hence in-memory wear leveling is an important requirement for practical applicability. Since writes to the stack often target a small and dense memory region, generic, coarse-grained wear-leveling mechanisms (e.g. virtual memory page remapping) are not sufficient. An alternative solution is to relocate the stack memory regularly, which involves copying of the stack content. As the stack content changes in size during the execution of an application, the copy overhead can be significantly mitigated by performing the relocation when the stack size is small. In this paper, we investigate two approaches to determine points in time when the stack is small. First, we analyze the possibility to fit simple machine-learning models to the stack usage function. Precise predictions of this function enable the identification of the minimum stack size during execution. In our evaluation, the tested models provide accurate estimates of the future stack usage function for a subset of common applications. As a second approach, we analyze applications a priori and determine potential optimal points to perform relocation in the instruction stream. In detail, we deploy the application in an analysis environment, which determines a rating for each executed instruction. Based on this rating, we apply a genetic algorithm to identify the best points in the instruction stream to perform the stack relocation. This approach allows to save up to 85% of the write overhead for wear-leveling in our experiments.
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| Mikail Yayla, Anas Toma, Kuan-Hsun Chen, Lenssen, Victoria Shpacovitch, Roland Hergenröder, Frank Weichert and Jian-Jia Chen.
Nanoparticle Classification Using Frequency Domain Analysis on Resource-Limited Platforms.
Journal of Sensors 19 4318
October 2019
[BibTeX][PDF][Link]@article { sensors-2019,
author = {Yayla, Mikail and Toma, Anas and Chen, Kuan-Hsun and Lenssen, and Shpacovitch, Victoria and Hergenr\"oder, Roland and Weichert, Frank and Chen, Jian-Jia},
date-added = {2019-11-15 21:41:55 +0000},
date-modified = {2019-11-15 21:45:29 +0000},
title = {Nanoparticle Classification Using Frequency Domain Analysis on Resource-Limited Platforms},
journal = {Journal of Sensors},
year = {2019},
volume = {19},
number = {4318},
month = {October},
url = {https://www.mdpi.com/1424-8220/19/19/4138},
keywords = {kuan},
file = {https://www.mdpi.com/1424-8220/19/19/4138/pdf},
confidential = {n},
} |
| Mikail Yayla, Anas Toma, Jan Eric Lenssen, Victoria Shpacovitch, Kuan-Hsun Chen, Frank Weichert and Jian-Jia Chen.
Resource-Efficient Nanoparticle Classification Using Frequency Domain Analysis.
In BVM Workshop
Lübeck, Germany, March 2019
[BibTeX][Abstract]@inproceedings { Yayla-BVM2019,
author = {Yayla, Mikail and Toma, Anas and Lenssen, Jan Eric and Shpacovitch, Victoria and Chen, Kuan-Hsun and Weichert, Frank and Chen, Jian-Jia},
title = {Resource-Efficient Nanoparticle Classification Using Frequency Domain Analysis},
booktitle = {BVM Workshop},
year = {2019},
address = {L\"ubeck, Germany},
month = {March},
keywords = {kuan},
confidential = {n},
abstract = {We present a method for resource-efficient classification of nanoparticles such as viruses in liquid or gas samples by analyzing Surface Plasmon Resonance (SPR) images using frequency domain features. The SPR images are obtained with the Plasmon Assisted Microscopy Of Nano-sized Objects (PAMONO) biosensor, which was developed as a mobile virus and particle detector. Convolutional neural network (CNN) solutions are available for the given task, but since the mobility of the sensor is an important factor, we provide a faster and less resource demanding alternative approach for the use in a small virus detection device.The execution time of our approach, which can be optimized further using low power hardware such as a digital signal processor (DSP), is at least 2.6 times faster than the current CNN solution while sacrificing only 1 to 2.5 percent points in accuracy.},
}
We present a method for resource-efficient classification of nanoparticles such as viruses in liquid or gas samples by analyzing Surface Plasmon Resonance (SPR) images using frequency domain features. The SPR images are obtained with the Plasmon Assisted Microscopy Of Nano-sized Objects (PAMONO) biosensor, which was developed as a mobile virus and particle detector. Convolutional neural network (CNN) solutions are available for the given task, but since the mobility of the sensor is an important factor, we provide a faster and less resource demanding alternative approach for the use in a small virus detection device.The execution time of our approach, which can be optimized further using low power hardware such as a digital signal processor (DSP), is at least 2.6 times faster than the current CNN solution while sacrificing only 1 to 2.5 percent points in accuracy.
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