@inproceedings { yayla/etal/2021,
  author = {Yayla, Mikail and Chen, Kuan-Hsun and Zervakis, Georgios and Henkel, J\"org and Chen, Jian-Jia and Amrouch, Hussam},
  title = {FeFET and NCFET for Future Neural Networks: Visions and Opportunities},
  booktitle = {Design, Automation and Test in Europe Conference (DATE)},
  year = {2021},
  keywords = {kuan, nvm-oma},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2021datefefet.pdf},
  confidential = {n},
  abstract = {The goal of this special session paper is to introduce and discuss different emerging technologies for logic circuitry and memory as well as new lightweight architectures for neural networks. We demonstrate how the ever-increasing complexity in Artificial Intelligent (AI) applications, resulting in an immense increase in the computational power, necessitates inevitably employing innovations starting from the underlying devices all the way up to the architectures. Two different promising emerging technologies will be presented: (i) Negative Capacitance Field-Effect Transistor (NCFET) as a new beyond-CMOS technology with advantages for offering low power and/or higher accuracy for neural network inference. (ii) Ferroelectric FET (FeFET) as a novel non-volatile, area-efficient and ultra-low power memory device. In addition, we demonstrate how Binary Neural Networks (BNNs) offer a promising alternative for traditional Deep Neural Networks (DNNs) due to its lightweight hardware implementation. Finally, we present the challenges from combining FeFET-based NVM with NNs and summarize our perspectives for future NNs and the vital role that emerging technologies may play.},
}

@inproceedings { buschjaegerSLOHA2021,
  author = {Buschj\"ager, Sebastian and Chen, Jian-Jia and Chen, Kuan-Hsun and G\"unzel, Mario and Morik, Katharina and Novkin, Rodion and Pfahler, Lukas and Yayla, Mikail},
  title = {Bit Error Tolerance Metrics for Binarized Neural Networks},
  booktitle = {Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA)},
  year = {2021},
  url = {https://arxiv.org/abs/2102.00818},
  keywords = {kuan},
  confidential = {n},
  abstract = {To reduce the resource demand of neural network (NN) inference systems, it has been proposed to use approximate
memory, in which the supply voltage and the timing parameters are tuned trading accuracy with energy consumption and performance. Tuning these parameters aggressively leads to bit errors, which can be tolerated by NNs when bit flips are injected during training. However, bit flip training, which is the state of the art for achieving bit error tolerance, does not scale well; it leads to massive overheads and cannot be applied for high bit error rates (BERs). Alternative methods to achieve bit error tolerance in NNs are needed, but the underlying principles behind the bit error tolerance of NNs have not been reported yet. With this lack of understanding, further progress in the research on NN bit error tolerance will be restrained.

In this study, our objective is to investigate the internal changes in the NNs that bit flip training causes, with a focus on  Binarized NNs (BNNs). To this end, we quantify the properties of bit error tolerant BNNs with two metrics. First, we propose a neuron-level bit error tolerance metric, which calculates the margin between the pre-activation values and batch normalization thresholds. Secondly, to capture the effects of bit error tolerance on the interplay of neurons, we propose an inter-neuron bit error tolerance metric, which measures the importance of each neuron and computes the variance over all importance values. Our experimental results support that these two metrics are strongly related to bit error tolerance.},
}

@inproceedings { buschjaeger/etal/2021,
  author = {Buschj\"ager, Sebastian and Chen, Jian-Jia and Chen, Kuan-Hsun and G\"unzel, Mario and Hakert, Christian and Morik, Katharina and Novkin, Rodion and Pfahler, Lukas and Yayla, Mikail},
  title = {Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance},
  booktitle = {Design, Automation and Test in Europe Conference (DATE), accepted},
  year = {2021},
  note = {Best Paper Award Candidate},
  keywords = {kuan, nvm-oma},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2021dateyayla.pdf},
  confidential = {n},
  abstract = {To overcome the memory wall in neural network (NN) inference systems, recent studies have proposed to use approximate memory, in which the supply voltage and access latency parameters are tuned, for lower energy consumption and faster access at the cost of reliability. To tolerate the occuring bit errors, the state-of-the-art approaches apply bit flip injections to the NNs during training, which require high overheads and do not scale well for large NNs and high bit error rates. In this work, we focus on binarized NNs (BNNs), whose simpler structure allows better exploration of bit error tolerance metrics based on margins. We provide formal proofs to quantify the maximum number of bit flips that can be tolerated. With the proposed margin-based metrics and the well-known hinge loss for maximum margin classification in support vector machines (SVMs), we are able to construct a modified hinge loss (MHL) to train BNNs for bit error tolerance without any bit flip injections. Our experimental results indicate that the MHL enables the possibility for BNNs to tolerate higher bit error rates than with bit flip training and, therefore, allows to further lower the requirements on approximate memories used for BNNs. },
}

@inproceedings { nvmsimulator,
  author = {Hakert, Christian and Chen, Kuan-Hsun and Yayla, Mikail and Br\"uggen, Georg von der and Bloemeke, Sebastian and Chen, Jian-Jia},
  title = {Software-Based Memory Analysis Environments for In-Memory Wear-Leveling},
  booktitle = {25th Asia and South Pacific Design Automation Conference ASP-DAC 2020, Invited Paper},
  year = {2020},
  address = {Beijing, China},
  keywords = {kuan, nvm-oma, georg},
  file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2020-aspdac-nvm.pdf},
  confidential = {n},
  abstract = {Emerging non-volatile memory (NVM) architectures are considered as a replacement for DRAM and storage in the near future, since NVMs provide low power consumption, fast access speed, and low unit cost. Due to the lower write-endurance of NVMs, several in-memory wear-leveling techniques have been studied over the last years. Since most approaches propose or rely on specialized hardware, the techniques are often evaluated based on assumptions and in-house simulations rather than on real systems. To address this issue, we develop a setup consisting of a gem5 instance and an NVMain2.0 instance, which simulates an entire system (CPU, peripherals, etc.) together with an NVM plugged into the system. Taking a recorded memory access pattern from a low-level simulation into consideration to design and optimize wear-leveling techniques as operating system services allows a cross-layer design of wear- leveling techniques. With the insights gathered by analyzing the recorded memory access patterns, we develop a software-only wear-leveling solution, which does not require special hardware at all. This algorithm is evaluated afterwards by the full system simulation.},
}

@article { buschjger2020explainable,
  author = {Buschj\"ager, Sebastian and Chen, Jian-Jia and Chen, Kuan-Hsun and G\"unzel, Mario and Hakert, Christian and Morik, Katharina and Novkin, Rodion and Pfahler, Lukas and Yayla, Mikail},
  title = {Towards Explainable Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks},
  journal = {CoRR},
  year = {2020},
  volume = {abs/2002.00909},
  url = {https://arxiv.org/pdf/2002.00909.pdf},
  keywords = {kuan, nvm-oma, mario},
  confidential = {n},
  abstract = {Non-volatile memory, such as resistive RAM (RRAM), is an emerging energy-efficient storage, especially for low-power machine learning models on the edge. It is reported, however, that the bit error rate of RRAMs can be up to 3.3% in the ultra low-power setting, which might be crucial for many use cases. Binary neural networks (BNNs), a resource efficient variant of neural networks (NNs), can tolerate a certain percentage of errors without a loss in accuracy and demand lower resources in computation and storage. The bit error tolerance (BET) in BNNs can be achieved by flipping the weight signs during training, as proposed by Hirtzlin et al., but their method has a significant drawback, especially for fully connected neural networks (FCNN): The FCNNs overfit to the error rate used in training, which leads to low accuracy under lower error rates. In addition, the underlying principles of BET are not investigated. In this work, we improve the training for BET of BNNs and aim to explain this property. We propose straight-through gradient approximation to improve the weight-sign-flip training, by which BNNs adapt less to the bit error rates. To explain the achieved robustness, we define a metric that aims to measure BET without fault injection. We evaluate the metric and find that it correlates with accuracy over error rate for all FCNNs tested. Finally, we explore the influence of a novel regularizer that optimizes with respect to this metric, with the aim of providing a configurable trade-off in accuracy and BET.},
}

@mastersthesis { 2019-yayla,
  title = {Resource-Aware Acceleration for Nano Particle Classification},
  author = {Yayla, Mikail},
  school = {TU Dortmund},
  year = {2019},
  file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/2019-yayla.pdf},
  confidential = {n},
  adviser = {Prof. Dr. Jian-Jia Chen and Dr. Kuan-Hsun Chen},
}

@inproceedings { mlcad2019stackanalysis,
  author = {Hakert, Christian and Yayla, Mikail and Chen, Kuan-Hsun and Br\"uggen, Georg von der and Chen, Jian-Jia and Buschj\"ager, Sebastian and Morik, Katharina and Genssler, Paul R. and Bauer, Lars and Amrouch, Hussam and Henkel, J\"org},
  title = {Stack Usage Analysis for Efficient Wear Leveling in Non-Volatile Main Memory Systems},
  booktitle = {1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)},
  year = {2019},
  address = {Alberta, Canada},
  keywords = {kuan, nvm-oma, georg},
  file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/mlcad_2019.pdf},
  confidential = {n},
  abstract = {Emerging non-volatile memory (NVM) technologies, such as Phase Change Memory (PCM), have been considered as a replacement for DRAM and storage due to their low power consumption, fast access speed, and low unit cost. Even so, some NVMs have a significantly lower write endurance and hence in-memory wear leveling is an important requirement for practical applicability. Since writes to the stack often target a small and dense memory region, generic, coarse-grained wear-leveling mechanisms (e.g. virtual memory page remapping) are not sufficient. An alternative solution is to relocate the stack memory regularly, which involves copying of the stack content. As the stack content changes in size during the execution of an application, the copy overhead can be significantly mitigated by performing the relocation when the stack size is small. In this paper, we investigate two approaches to determine points in time when the stack is small. First, we analyze the possibility to fit simple machine-learning models to the stack usage function. Precise predictions of this function enable the identification of the minimum stack size during execution. In our evaluation, the tested models provide accurate estimates of the future stack usage function for a subset of common applications. As a second approach, we analyze applications a priori and determine potential optimal points to perform relocation in the instruction stream. In detail, we deploy the application in an analysis environment, which determines a rating for each executed instruction. Based on this rating, we apply a genetic algorithm to identify the best points in the instruction stream to perform the stack relocation. This approach allows to save up to 85% of the write overhead for wear-leveling in our experiments.},
}

@article { sensors-2019,
  author = {Yayla, Mikail and Toma, Anas and Chen, Kuan-Hsun and Lenssen, and Shpacovitch, Victoria and Hergenr\"oder, Roland and Weichert, Frank and Chen, Jian-Jia},
  date-added = {2019-11-15 21:41:55 +0000},
  date-modified = {2019-11-15 21:45:29 +0000},
  title = {Nanoparticle Classification Using Frequency Domain Analysis on Resource-Limited Platforms},
  journal = {Journal of Sensors},
  year = {2019},
  volume = {19},
  number = {4318},
  month = {October},
  url = {https://www.mdpi.com/1424-8220/19/19/4138},
  keywords = {kuan},
  file = {https://www.mdpi.com/1424-8220/19/19/4138/pdf},
  confidential = {n},
}

@inproceedings { Yayla-BVM2019,
  author = {Yayla, Mikail and Toma, Anas and Lenssen, Jan Eric and Shpacovitch, Victoria and Chen, Kuan-Hsun and Weichert, Frank and Chen, Jian-Jia},
  title = {Resource-Efficient Nanoparticle Classification Using Frequency Domain Analysis},
  booktitle = {BVM Workshop},
  year = {2019},
  address = {L\"ubeck, Germany},
  month = {March},
  keywords = {kuan},
  confidential = {n},
  abstract = {We present a method for resource-efficient classification of nanoparticles such as viruses in liquid or gas samples by analyzing Surface Plasmon Resonance (SPR) images using frequency domain features. The SPR images are obtained with the Plasmon Assisted Microscopy Of Nano-sized Objects (PAMONO) biosensor, which was developed as a mobile virus and particle detector. Convolutional neural network (CNN) solutions are available for the given task, but since the mobility of the sensor is an important factor, we provide a faster and less resource demanding alternative approach for the use in a small virus detection device.The execution time of our approach, which can be optimized further using low power hardware such as a digital signal processor (DSP), is at least 2.6 times faster than the current CNN solution while sacrificing only 1 to 2.5 percent points in accuracy.},
}

@inproceedings { Yayla2018EITEC,
  author = {Yayla, Mikail and Chen, Kuan-Hsun and Chen, Jian-Jia},
  title = {Fault Tolerance on Control Applications: Empirical Investigations of Impacts from Incorrect Calculations},
  booktitle = {4th Workshop on Emerging Ideas and Trends in Engineering of Cyber-Physical Systems (EITEC)},
  year = {2018},
  url = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2018-yayla-eitec.pdf},
  keywords = {kuan},
  confidential = {n},
  abstract = {Due to aggressive technology downscaling, mobile and embedded systems are susceptible to transient faults in the underlying hardware. Transient faults may incur soft-errors or even lead to system failure. A recent study has proposed to exploit the concept of the (m,k)-firm real-time task model with compensation techniques to manage redundant executions, aiming to selectively protect the control application. In this work we provide an empirical approach to find the (m,k) robustness requirements. With the delivered (m,k) robustness requirements on path tracing and balance control tasks, we conduct comprehensive case studies to evaluate the effectiveness of the compensation techniques under different fault locations and fault rates. },
}

@bachelorthesis { yayla:2017,
  title = {Deep Investigation for Fault Tolerance and Soft-Error Handling on Control Application},
  author = {Yayla, Mikail},
  year = {2017},
  month = {March},
  note = {The enhancement of the thesis has been added in the downloadable version.},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/yayla.pdf},
  confidential = {n},
  adviser = {Prof. Dr. Jian-Jia Chen, M.Sc. Kuan-Hsun Chen},
}