Hauptinhalt
Completed Theses at DAES Group (Bachelor, Master, PhD)
2020
- Xiaoshi Wang:
Analysis and Optimization for Hoeffding Tree.
2020, B.Sc. thesis, Adviser: Dr.-Ing. Kuan-Hsun Chen, Prof. Dr. Jian-Jia Chen
[BibTeX]@bachelorthesis { wang2020,
title = {Analysis and Optimization for Hoeffding Tree},
author = {Wang, Xiaoshi},
school = {TU Dortmund},
year = {2020},
keywords = {thesis},
confidential = {n},
adviser = {Dr.-Ing. Kuan-Hsun Chen, Prof. Dr. Jian-Jia Chen},
}
- Giancarlo Stooß:
Exploring the Health of Automotive Systems under Transient and Intermittent Faults.
2020, B.Sc. thesis, Adviser: Jian-JIa Chen and Lea Schönberger
[BibTeX]@bachelorthesis { Stooss2020,
title = {Exploring the Health of Automotive Systems under Transient and Intermittent Faults},
author = {Stoo\"s, Giancarlo},
school = {TU Dortmund University},
year = {2020},
confidential = {n},
adviser = {Jian-JIa Chen and Lea Sch\"onberger},
}
- Aaron Larisch:
An efficient real-time capable multi-core module framework for the humanoid robot NAO.
2020, M.Sc. thesis, Adviser: Prof. Dr. Uwe Schwiegelshohn, Prof. Dr. Jian-Jia Chen, Dipl.-Inf. Ingmar Schwarz
[BibTeX]@mastersthesis { larisch2020,
title = {An efficient real-time capable multi-core module framework for the humanoid robot NAO},
author = {Larisch, Aaron},
school = {TU Dortmund},
year = {2020},
confidential = {n},
adviser = {Prof. Dr. Uwe Schwiegelshohn, Prof. Dr. Jian-Jia Chen, Dipl.-Inf. Ingmar Schwarz},
}
- Roman Sazontow:
Supporting Edge Computing Simulator for Real-Time Task models.
2020, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, Dr.-Ing. Kuan-Hsun Chen
[BibTeX][Abstract]@bachelorthesis { Sazontow2020,
title = {Supporting Edge Computing Simulator for Real-Time Task models},
author = {Sazontow, Roman},
school = {TU Dortmund},
year = {2020},
keywords = {Edge Computing, Cloud computing, Simulation, Real-Time Systems},
confidential = {n},
abstract = {Edge computing is a fast growing field of research and is becoming more relevant recently.
Due to increasing data size, cloud computing is not as efficient anymore. It is faster and
more efficient to process the data at the edge of the network rather than in the cloud.
In order to test simulations in such environments, EdgeCloudSim was developed by C.
Sonmez et al. [13] EdgeCloudSim is an extension of CloudSim and serves as a simulation
tool for edge computing scenarios. It simulates mobile devices that move between various
access points and creates tasks that have to be efficiently distributed and executed. In its
current design, EdgeCloudSim does not support Real-Time task models. Real-Time is a
relevant part of edge computing, since edge computing is a computing paradigm that offers
fast response times, which are important for Real-Time scenarios. Similar to normal
edge computing scenarios, it is desirable to have a simulation tool that can be used to
test Real-Time edge computing systems. The purpose of this bachelor thesis is to extend
EdgeCloudSim by adding Real-Time support. In order to do so, the necessary Real-Time
characteristics have to be added to the source code.
},
adviser = {Prof. Dr. Jian-Jia Chen, Dr.-Ing. Kuan-Hsun Chen},
}
Edge computing is a fast growing field of research and is becoming more relevant recently.
Due to increasing data size, cloud computing is not as efficient anymore. It is faster and
more efficient to process the data at the edge of the network rather than in the cloud.
In order to test simulations in such environments, EdgeCloudSim was developed by C.
Sonmez et al. [13] EdgeCloudSim is an extension of CloudSim and serves as a simulation
tool for edge computing scenarios. It simulates mobile devices that move between various
access points and creates tasks that have to be efficiently distributed and executed. In its
current design, EdgeCloudSim does not support Real-Time task models. Real-Time is a
relevant part of edge computing, since edge computing is a computing paradigm that offers
fast response times, which are important for Real-Time scenarios. Similar to normal
edge computing scenarios, it is desirable to have a simulation tool that can be used to
test Real-Time edge computing systems. The purpose of this bachelor thesis is to extend
EdgeCloudSim by adding Real-Time support. In order to do so, the necessary Real-Time
characteristics have to be added to the source code.
- Dennis Morczinek:
Configurable FPGA-based Access Latency Emulation for Non-Volatile Main Memory.
2020, B.Sc. thesis, Adviser: Christian Hakert
[BibTeX][Abstract]@bachelorthesis { morczinek2020ba,
title = {Configurable FPGA-based Access Latency Emulation for Non-Volatile Main Memory},
author = {Morczinek, Dennis},
school = {TU Dortmund},
year = {2020},
keywords = {nvm-oma},
confidential = {n},
abstract = {Since the drawbacks of using non-volatile memory (NVM) technologies as main memory
are being addressed by researchers, its use as an energy efficient alternative to traditional
DRAM is more interesting than ever. The impact of the greater memory access latencies
of NVM compared to DRAM on a system can be investigated in systems that utilize at
least one type of NVM as main memory. In many cases those systems do not exist yet,
so the research has to be conducted on non-volatile main memory (NVMM) emulators or
simulators. Yu Omori et al. developed such an emulator on an SoC-FPGA. Their emulator
injects additional read and write delays to memory accesses that are configurable by the
user. However, the configurations are applied to the whole memory of the emulator, so
emulating hybrid systems with more than one NVMM type is not possible.
This thesis extends the FPGA emulator design of Yu Omori et al. to allow the emulation
of more than one NVMM type by making it possible to define areas in the main memory
with different access latencies. The underlying emulator architecture is adapted so that
the corresponding latency for each area can be stored and the delay injection logic receives
the appropriate value when a memory access is performed. The count of definable areas
and the utilization of the FPGA are kept in balance to allow for future modifications of
the emulator design.
},
adviser = {Christian Hakert},
}
Since the drawbacks of using non-volatile memory (NVM) technologies as main memory
are being addressed by researchers, its use as an energy efficient alternative to traditional
DRAM is more interesting than ever. The impact of the greater memory access latencies
of NVM compared to DRAM on a system can be investigated in systems that utilize at
least one type of NVM as main memory. In many cases those systems do not exist yet,
so the research has to be conducted on non-volatile main memory (NVMM) emulators or
simulators. Yu Omori et al. developed such an emulator on an SoC-FPGA. Their emulator
injects additional read and write delays to memory accesses that are configurable by the
user. However, the configurations are applied to the whole memory of the emulator, so
emulating hybrid systems with more than one NVMM type is not possible.
This thesis extends the FPGA emulator design of Yu Omori et al. to allow the emulation
of more than one NVMM type by making it possible to define areas in the main memory
with different access latencies. The underlying emulator architecture is adapted so that
the corresponding latency for each area can be stored and the delay injection logic receives
the appropriate value when a memory access is performed. The count of definable areas
and the utilization of the FPGA are kept in balance to allow for future modifications of
the emulator design.
- Junior Delrich Kamtchogom Namtchueng:
Extendable Hardware-Based Main Memory Access Snooping for Non-volatile Memory Simulations and Analysis.
2020, B.Sc. thesis, Adviser: Christian Hakert
[BibTeX][Abstract]@bachelorthesis { kamtchogom2020ba,
title = {Extendable Hardware-Based Main Memory Access Snooping for Non-volatile Memory Simulations and Analysis},
author = {Namtchueng, Junior Delrich Kamtchogom},
school = {TU Dortmund},
year = {2020},
keywords = {nvm-oma},
confidential = {n},
abstract = {In order to determine the internal functioning of a computer memory, a simulation is
necessary. Simulate a memory means, make read/write requests to this memory and
observe the path that the requests are going through. Knowledges about the internal
functioning is for example important to be able to give some guarantees about its latency
or its reponse time. Make this simulation implicitly means the need of a simulator.
This thesis is about designing the simulator by using an extension hardware interface of
the processor and then analysing the output values of the simulator.
The methodology followed here is, first the presentation of the hardware interface, then
the presentation of the dataflow during the different requests, then the presentation of the
design used for the simulation and finally the analysis of the simulation result.
The analysis of the simulation result showed that both part of the memory (registers and
BRAM) simulated here work perfectly. In addition, during the access to the BRAM, it
results a delay between the moment when it receives the request and the moment when
it returns a response. Beyond that, the registers and the BRAM have in common that
they have a small addressable space. To have an access to a larger space another means
(DRAM access) is slightly described.
},
adviser = {Christian Hakert},
}
In order to determine the internal functioning of a computer memory, a simulation is
necessary. Simulate a memory means, make read/write requests to this memory and
observe the path that the requests are going through. Knowledges about the internal
functioning is for example important to be able to give some guarantees about its latency
or its reponse time. Make this simulation implicitly means the need of a simulator.
This thesis is about designing the simulator by using an extension hardware interface of
the processor and then analysing the output values of the simulator.
The methodology followed here is, first the presentation of the hardware interface, then
the presentation of the dataflow during the different requests, then the presentation of the
design used for the simulation and finally the analysis of the simulation result.
The analysis of the simulation result showed that both part of the memory (registers and
BRAM) simulated here work perfectly. In addition, during the access to the BRAM, it
results a delay between the moment when it receives the request and the moment when
it returns a response. Beyond that, the registers and the BRAM have in common that
they have a small addressable space. To have an access to a larger space another means
(DRAM access) is slightly described.
- Waldemar Seiferling:
Meta Machine Learning Optimization: Cache-aware Organization of Decision Trees.
2020, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, Dr.-Ing. Kuan-Hsun Chen
[BibTeX][Abstract]@bachelorthesis { swiferlingBA2020,
title = {Meta Machine Learning Optimization: Cache-aware Organization of Decision Trees},
author = {Seiferling, Waldemar},
school = {TU Dortmund},
year = {2020},
confidential = {n},
abstract = {The purpose of this thesis is to present ways to optimize the execution of decision trees. The focus will be to optimize the cache performance using the genetic algorithm approach. In this way the decision tree execution becomes cache aware and offers theoretically better execution speed. In the thesis at first basic technologies will be explained. This includes explaining the implementation of decision trees and it's memory layout and how it can be changed. The memory layout is most significant for the cache performance. An implementation will be presented of a genetic algorithm which changes the decision tree memory layout by swapping of memory addresses of nodes and selection of best memory layout using execution results and other methods. Cache misses of different memory layouts will be compared to select to select best candidates. Understanding how cache works will be also looked into. Modern processors are using caches to hide performance differences of the CPU and main memory which also affects the execution of decision trees. The genetic algorithm will be using a cache simulator for its fitness function. Different cache performance pro ling tools which oer counters to measure cache misses will be tested. The implemented algorithms will be tested on different computers to compare the results.
},
adviser = {Prof. Dr. Jian-Jia Chen, Dr.-Ing. Kuan-Hsun Chen},
}
The purpose of this thesis is to present ways to optimize the execution of decision trees. The focus will be to optimize the cache performance using the genetic algorithm approach. In this way the decision tree execution becomes cache aware and offers theoretically better execution speed. In the thesis at first basic technologies will be explained. This includes explaining the implementation of decision trees and it's memory layout and how it can be changed. The memory layout is most significant for the cache performance. An implementation will be presented of a genetic algorithm which changes the decision tree memory layout by swapping of memory addresses of nodes and selection of best memory layout using execution results and other methods. Cache misses of different memory layouts will be compared to select to select best candidates. Understanding how cache works will be also looked into. Modern processors are using caches to hide performance differences of the CPU and main memory which also affects the execution of decision trees. The genetic algorithm will be using a cache simulator for its fitness function. Different cache performance pro ling tools which oer counters to measure cache misses will be tested. The implemented algorithms will be tested on different computers to compare the results.
- Felix Mues:
Optimization of OpenGL streaming in distributed embedded systems.
June 2020, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, Dr. Robert Budde
[BibTeX]@bachelorthesis { Mues2020,
title = {Optimization of OpenGL streaming in distributed embedded systems},
author = {Mues, Felix},
school = {TU Dortmund},
year = {2020},
month = {June},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, Dr. Robert Budde},
}
- Nikolas Müller:
3D-Sensor-Data-based Localization of Logistical Objects with Machine Learning on Embedded Systems.
April 2020, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, Dr. Sören Kerner
[BibTeX][Abstract]@mastersthesis { mueller2020,
title = {3D-Sensor-Data-based Localization of Logistical Objects with Machine Learning on Embedded Systems},
author = {Müller, Nikolas},
school = {TU Dortmund},
year = {2020},
month = {April},
confidential = {n},
abstract = {Localization of objects in cluttered scenes with machine learning methods is a fairly
young research area. Especially for logistical environments, there has not been much
published work on that topic. Despite the high potential of object localization for
full process automation in Industry 4.0, data sets for such applications, to train and
test machine learning models, are not openly available.
Although the recent hype around neural feedforward networks has covered a lot of
research topics, it mostly focused on 1D- and 2D-sensor-signals in the form of audio
and images, while spatial 3D-sensor data, which would allow such an accurate object
localization, remained mostly untouched. In this thesis, a full solution is provided on
how to localize logistical objects in isolated 3D-sensor scans. It utilizes feedforward
networks and ranges from the generation of the training data for the networks, over
the detection of objects in the 3D-sensor data, up to the estimation of the object
poses for the detected objects. To generate sample training data of 3D-sensors, a
novel method is proposed, which allows the training of feedforward networks in con-
text of logistical environments in a self-supervised manner by simulating 3D-sensor
scans of randomly generated, but structurally valid scenes. Meanwhile, for the ob-
ject detection and pose estimation, some known solutions from similar problems are
inspected, compared, combined, and optimized, to present a new approach to solve
the given task. Hereby, resource limitations during the execution of the proposed
solution are considered, as in many mobile use-cases such an object localization has
to run efficiently on an embedded system.
The here presented method is able to reliably detect logistical objects of indefinite
amounts at 5 frames per second in a sequential operation on an NVIDIA Jetson
AGX Xavier, while consuming 12.4W of power on average. As in related work, the
pose estimation is not precise enough for symmetric objects. However, at the end of
this thesis, some possible improvements for the solution are proposed to reduce the
run-time and increase the accuracy of the entire system.
},
adviser = {Prof. Dr. Jian-Jia Chen, Dr. Sören Kerner},
}
Localization of objects in cluttered scenes with machine learning methods is a fairly
young research area. Especially for logistical environments, there has not been much
published work on that topic. Despite the high potential of object localization for
full process automation in Industry 4.0, data sets for such applications, to train and
test machine learning models, are not openly available.
Although the recent hype around neural feedforward networks has covered a lot of
research topics, it mostly focused on 1D- and 2D-sensor-signals in the form of audio
and images, while spatial 3D-sensor data, which would allow such an accurate object
localization, remained mostly untouched. In this thesis, a full solution is provided on
how to localize logistical objects in isolated 3D-sensor scans. It utilizes feedforward
networks and ranges from the generation of the training data for the networks, over
the detection of objects in the 3D-sensor data, up to the estimation of the object
poses for the detected objects. To generate sample training data of 3D-sensors, a
novel method is proposed, which allows the training of feedforward networks in con-
text of logistical environments in a self-supervised manner by simulating 3D-sensor
scans of randomly generated, but structurally valid scenes. Meanwhile, for the ob-
ject detection and pose estimation, some known solutions from similar problems are
inspected, compared, combined, and optimized, to present a new approach to solve
the given task. Hereby, resource limitations during the execution of the proposed
solution are considered, as in many mobile use-cases such an object localization has
to run efficiently on an embedded system.
The here presented method is able to reliably detect logistical objects of indefinite
amounts at 5 frames per second in a sequential operation on an NVIDIA Jetson
AGX Xavier, while consuming 12.4W of power on average. As in related work, the
pose estimation is not precise enough for symmetric objects. However, at the end of
this thesis, some possible improvements for the solution are proposed to reduce the
run-time and increase the accuracy of the entire system.
2019
- Jan Duy Thien Pham:
Supporting Semi-Partitioned Multiprocessor Resource Synchronization Protocols on RTEMS.
2019, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and M.Sc Junjie Shi
[BibTeX][Abstract]@bachelorthesis { Pha19,
title = {Supporting Semi-Partitioned Multiprocessor Resource Synchronization Protocols on RTEMS},
author = {Pham, Jan Duy Thien},
school = {TU Dortmund},
year = {2019},
confidential = {n},
abstract = {Managing resource accesses of tasks is one of the most important aspects of a real-time
operating system. For uniprocessor systems, there are many solutions in form of resource
synchronization protocols commonly in use. One of them is the Priority Ceiling Protocol
(PCP). While pure PCP works well on a uniprocessor system, it runs into problems when
transitioning to a multiprocessor system. Thus many multiprocessor resource synchro-
nization protocols have been proposed in the literature. However of these protocols, only
a handful of them a implemented on real systems.
Hence in this thesis, we implemented three multiprocessor resource synchronization pro-
tocols: Distributed Priority Ceiling Protocol (DPCP), the Distributed Flexible Lock-
ing Protocol Long (DFLPL) and the Dependency Graph Approach for Periodic Tasks
(HDGA) on the real-time operating system Real-Time Executive for Multiprocessor Sys-
tems (RTEMS). These protocols support a semi-partitioned scheduling, where tasks can
migrate to a different processor under predefined criteria. We evaluated our implementa-
tions by measuring the overheads. The results show that our new implemented protocols
have comparable overheads with the existing protocols.},
adviser = {Prof. Dr. Jian-Jia Chen and M.Sc Junjie Shi},
}
Managing resource accesses of tasks is one of the most important aspects of a real-time
operating system. For uniprocessor systems, there are many solutions in form of resource
synchronization protocols commonly in use. One of them is the Priority Ceiling Protocol
(PCP). While pure PCP works well on a uniprocessor system, it runs into problems when
transitioning to a multiprocessor system. Thus many multiprocessor resource synchro-
nization protocols have been proposed in the literature. However of these protocols, only
a handful of them a implemented on real systems.
Hence in this thesis, we implemented three multiprocessor resource synchronization pro-
tocols: Distributed Priority Ceiling Protocol (DPCP), the Distributed Flexible Lock-
ing Protocol Long (DFLPL) and the Dependency Graph Approach for Periodic Tasks
(HDGA) on the real-time operating system Real-Time Executive for Multiprocessor Sys-
tems (RTEMS). These protocols support a semi-partitioned scheduling, where tasks can
migrate to a different processor under predefined criteria. We evaluated our implementa-
tions by measuring the overheads. The results show that our new implemented protocols
have comparable overheads with the existing protocols.
- Harun Teper:
Navigation mobiler Roboter mit dynamischen Hindernissen.
2019, B.Sc. thesis, Adviser: Niklas Ueter
[BibTeX]@bachelorthesis { teperba,
title = {Navigation mobiler Roboter mit dynamischen Hindernissen},
author = {Teper, Harun},
school = {TU Dortmund},
year = {2019},
confidential = {n},
adviser = {Niklas Ueter},
}
- Christian Hakert:
Memory Access Analysis and Endurance Leveling Approaches for Non-volatile Working Memory Systems.
2019, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr. Kuan-Hsun Chen
[BibTeX][Abstract]@mastersthesis { HakertMA,
title = {Memory Access Analysis and Endurance Leveling Approaches for Non-volatile Working Memory Systems},
author = {Hakert, Christian},
school = {TU Dortmund},
year = {2019},
keywords = {nvm-oma},
confidential = {n},
abstract = {Emerging technologies for non-volatile memory (NVM), such as phase-change memory (PCM), ferroelectric RAM (FeRAM), spin-transfer torque magnetoresistive RAM (STT-MRAM) and many more, have been considered as a replacement for DRAM and storage due to low leakage power, high capacity and fast access times. A major disadvantage of some NVMs is the significantly lower write endurance compared to DRAM. To tackle this issue, several in-memory wear-leveling approaches have been proposed in literature, targeting the program execution to make the memory write usage more uniform. These approaches operate on different granularities, like memory pages, cache-lines, big segments, etc. Aging-aware approaches take the current wear-level of memory cells into account to make the best wear-leveling decisions, while other approaches try to balance the wear-level in a random based manner or in a circular manner. However, most approaches propose specialized hardware controllers to collect the aging information and to perform wear-leveling actions, like relocations of memory regions.
As specialized hardware may be hard to build at all, this thesis proposes so-called software only wear-leveling, which only makes use of commonly available hardware components. Aging-aware wear-leveling on the granularity of virtual memory pages is achieved by estimating the cell aging by a statistical runtime approximation. As an extension to this, fine-grained wear-leveling for the stack region of applications is achieved by relocating the stack periodically in a circular manner through a reserved memory region.
The necessity for commonly available hardware components only allows the techniques to be executed in a full system simulation setup (i.e. gem5 as a simulator for an ARM CPU and NVMain 2.0 as a simulator for the NVM) for evaluation purposes. The results show that coarse-grained aging-aware wear-leveling with approximated cell ages works out, but cannot resolve non-uniform write distributions within virtual memory pages. This limits the gained improvement of the memory lifetime up to a factor of ≈ 13 compared to the baseline without any wear-leveling. Combining the coarse-grained approach with the fine- grained stack wear-leveling technique, the non-uniformity caused by the stack region can be resolved and the evaluations result in an improvement of the memory lifetime up to a factor of ≈ 900 compared to the baseline.},
adviser = {Prof. Dr. Jian-Jia Chen and Dr. Kuan-Hsun Chen},
}
Emerging technologies for non-volatile memory (NVM), such as phase-change memory (PCM), ferroelectric RAM (FeRAM), spin-transfer torque magnetoresistive RAM (STT-MRAM) and many more, have been considered as a replacement for DRAM and storage due to low leakage power, high capacity and fast access times. A major disadvantage of some NVMs is the significantly lower write endurance compared to DRAM. To tackle this issue, several in-memory wear-leveling approaches have been proposed in literature, targeting the program execution to make the memory write usage more uniform. These approaches operate on different granularities, like memory pages, cache-lines, big segments, etc. Aging-aware approaches take the current wear-level of memory cells into account to make the best wear-leveling decisions, while other approaches try to balance the wear-level in a random based manner or in a circular manner. However, most approaches propose specialized hardware controllers to collect the aging information and to perform wear-leveling actions, like relocations of memory regions.
As specialized hardware may be hard to build at all, this thesis proposes so-called software only wear-leveling, which only makes use of commonly available hardware components. Aging-aware wear-leveling on the granularity of virtual memory pages is achieved by estimating the cell aging by a statistical runtime approximation. As an extension to this, fine-grained wear-leveling for the stack region of applications is achieved by relocating the stack periodically in a circular manner through a reserved memory region.
The necessity for commonly available hardware components only allows the techniques to be executed in a full system simulation setup (i.e. gem5 as a simulator for an ARM CPU and NVMain 2.0 as a simulator for the NVM) for evaluation purposes. The results show that coarse-grained aging-aware wear-leveling with approximated cell ages works out, but cannot resolve non-uniform write distributions within virtual memory pages. This limits the gained improvement of the memory lifetime up to a factor of ≈ 13 compared to the baseline without any wear-leveling. Combining the coarse-grained approach with the fine- grained stack wear-leveling technique, the non-uniformity caused by the stack region can be resolved and the evaluations result in an improvement of the memory lifetime up to a factor of ≈ 900 compared to the baseline.
- Kuan-Hsun Chen:
Optimization and analysis for dependable application software on unreliable hardware platforms.
2019, PhD thesis, Adviser: Prof. Dr. Jian-Jia Chen
[BibTeX][Link][Abstract]@phdthesis { khchenPhd,
title = {Optimization and analysis for dependable application software on unreliable hardware platforms},
author = {Chen, Kuan-Hsun},
school = {TU Dortmund},
year = {2019},
url = {https://eldorado.tu-dortmund.de/handle/2003/38110},
keywords = {Real-time systems, Fault tolerance, Embedded systems},
confidential = {n},
abstract = {As chip technology keeps on shrinking towards higher densities and lower operating voltages, memory and logic components are now vulnerable to electromagnetic inference and radiation, leading to transient faults in the underlying hardware, which may jeopardize the correctness of software execution and cause so-called soft errors. To mitigate threats of soft errors, embedded-software developers have started to deploy Software-Implemented Hardware Fault Tolerance (SIHFT) techniques. However, the main cost is the significant amount of time due to the additional computation of using SIHFT techniques. To support safety critical systems, e.g., computing systems in automotive and avionic devices, real-time system technology has been primarily used and been widely studied. While considering hardware transient faults and SIHFT techniques with real-time system technology, novel scheduling approaches and schedulability analyses are desired to provide a less pessimistic o -line guarantee for timeliness or at least to provide a certain degree of performance for new application models. Moreover, reliability
optimizations also need to be designed thoughtfully while considering different resource constraints.
In this dissertation, we present three treatments for soft errors. Firstly, we study how to allow erroneous computations without deadline misses by modeling inherent safety margins and noise tolerance in control applications as (m; k) constraints. We further discuss how a given (m; k) requirement can be satisfied by individual error detection and flexible compensations while satisfying the given hard real-time constraints. Secondly, we
analyze the probability of deadline misses and the deadline miss rate in soft real-time systems, which allow to have occasional deadline misses without erroneous computations. Thirdly, we consider how to deploy redundant multi-threading techniques to improve the system reliability under two different system models for multi-core systems: 1) Under core-to-core frequency variations, we address the reliability-aware task-mapping problem.
2) We decide on redundancy levels for each task while satisfying the given real-time constraints and the limited redundant cores even under multi-tasking. Finally, an enhancement for real time operating systems is also provided to maintain the strict periodicity for task overruns due to potential transient faults, especially on one popular platform named Real-Time Executive for Multiprocessor Systems (RTEMS).},
adviser = {Prof. Dr. Jian-Jia Chen},
}
As chip technology keeps on shrinking towards higher densities and lower operating voltages, memory and logic components are now vulnerable to electromagnetic inference and radiation, leading to transient faults in the underlying hardware, which may jeopardize the correctness of software execution and cause so-called soft errors. To mitigate threats of soft errors, embedded-software developers have started to deploy Software-Implemented Hardware Fault Tolerance (SIHFT) techniques. However, the main cost is the significant amount of time due to the additional computation of using SIHFT techniques. To support safety critical systems, e.g., computing systems in automotive and avionic devices, real-time system technology has been primarily used and been widely studied. While considering hardware transient faults and SIHFT techniques with real-time system technology, novel scheduling approaches and schedulability analyses are desired to provide a less pessimistic o -line guarantee for timeliness or at least to provide a certain degree of performance for new application models. Moreover, reliability
optimizations also need to be designed thoughtfully while considering different resource constraints.
In this dissertation, we present three treatments for soft errors. Firstly, we study how to allow erroneous computations without deadline misses by modeling inherent safety margins and noise tolerance in control applications as (m; k) constraints. We further discuss how a given (m; k) requirement can be satisfied by individual error detection and flexible compensations while satisfying the given hard real-time constraints. Secondly, we
analyze the probability of deadline misses and the deadline miss rate in soft real-time systems, which allow to have occasional deadline misses without erroneous computations. Thirdly, we consider how to deploy redundant multi-threading techniques to improve the system reliability under two different system models for multi-core systems: 1) Under core-to-core frequency variations, we address the reliability-aware task-mapping problem.
2) We decide on redundancy levels for each task while satisfying the given real-time constraints and the limited redundant cores even under multi-tasking. Finally, an enhancement for real time operating systems is also provided to maintain the strict periodicity for task overruns due to potential transient faults, especially on one popular platform named Real-Time Executive for Multiprocessor Systems (RTEMS).
- Mikail Yayla:
Resource-Aware Acceleration for Nano Particle Classification.
2019, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr. Kuan-Hsun Chen
[BibTeX]@mastersthesis { 2019-yayla,
title = {Resource-Aware Acceleration for Nano Particle Classification},
author = {Yayla, Mikail},
school = {TU Dortmund},
year = {2019},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen and Dr. Kuan-Hsun Chen},
}
- Jan Kaiser:
Towards Accurate Binary Object Detection in the Context of Industry 4.0.
2019, M.Sc. thesis, Adviser: Prof. Jian-Jia Chen, Dr. Kuan-Hsun Chen
[BibTeX]@mastersthesis { kaiser2019,
title = {Towards Accurate Binary Object Detection in the Context of Industry 4.0},
author = {Kaiser, Jan},
school = {TU Dortmund},
year = {2019},
confidential = {n},
adviser = {Prof. Jian-Jia Chen, Dr. Kuan-Hsun Chen},
}
- Sebastian Blömeke:
Analysis and Optimization of Trace-Based Simulator for Non-Volatile Main Memory.
2019, B.Sc. thesis, Adviser: Dr.-Ing Kuan-Hsun Chen, Prof. Dr. Jian-Jia Chen
[BibTeX][Abstract]@bachelorthesis { bloemeke2019,
title = {Analysis and Optimization of Trace-Based Simulator for Non-Volatile Main Memory},
author = {Bl\"omeke, Sebastian},
school = {TU Dortmund},
year = {2019},
keywords = {nvm-oma, thesis},
confidential = {n},
abstract = {In the last years, new Technologies for non-volatile memory (NVM) emerged as a replacement for storage and RAM, due to their fast access times, low leakage power and high capacity. Two recent examples would be spin transfer torque magnetoresistive RAM (STT-MRAM) [3] and phase change memory (PCM) like 3D-XPoint in Intels Optane Series. The major drawback of NVM especially as a replacement for RAM is the low write endurance. There are hardware and software solutions for this problem [4], however to test and validate them modified hardware or specialized simulation software is needed.
In academic research it is a popular choice to simulate a full hardware setup with the software gem5 or the behavior of NVM with the software NVMain, but even short simulations in NVMain will generate trace files of tens of gigabyte. The volume of the trace files is slowing down both the simulation speed and the post-processing of the results. In this thesis i will describe and implement some optimizations to NVMain’s trace file writer which will result in a 30% reduction of trace file volume without data loss and the option of filtering out unnecessary data fields.},
adviser = {Dr.-Ing Kuan-Hsun Chen, Prof. Dr. Jian-Jia Chen},
}
In the last years, new Technologies for non-volatile memory (NVM) emerged as a replacement for storage and RAM, due to their fast access times, low leakage power and high capacity. Two recent examples would be spin transfer torque magnetoresistive RAM (STT-MRAM) [3] and phase change memory (PCM) like 3D-XPoint in Intels Optane Series. The major drawback of NVM especially as a replacement for RAM is the low write endurance. There are hardware and software solutions for this problem [4], however to test and validate them modified hardware or specialized simulation software is needed.
In academic research it is a popular choice to simulate a full hardware setup with the software gem5 or the behavior of NVM with the software NVMain, but even short simulations in NVMain will generate trace files of tens of gigabyte. The volume of the trace files is slowing down both the simulation speed and the post-processing of the results. In this thesis i will describe and implement some optimizations to NVMain’s trace file writer which will result in a 30% reduction of trace file volume without data loss and the option of filtering out unnecessary data fields.
- Sebastian Schwitalla:
Priority-Preserving Optimization of Hardware Filter Efficiency for Broadcast Buses.
June 2019, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Lea Schönberger, M.Sc.
[BibTeX]@bachelorthesis { schwitalla2019,
title = {Priority-Preserving Optimization of Hardware Filter Efficiency for Broadcast Buses},
author = {Schwitalla, Sebastian},
school = {TU Dortmund University},
year = {2019},
month = {June},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen and Lea Sch\"onberger, M.Sc.},
}
- Iryna Denysenko:
Exploring the Performance of Hardware Message Filtering in Controller Area Network.
April 2019, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Lea Schönberger, M.Sc.
[BibTeX]@mastersthesis { denysenko2019,
title = {Exploring the Performance of Hardware Message Filtering in Controller Area Network},
author = {Denysenko, Iryna},
school = {TU Dortmund University},
year = {2019},
month = {April},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen and Lea Sch\"onberger, M.Sc.},
}
2018
- Andreas Lang:
Ablaufplanungsverfahren zur effizienten Ressourcennutzung bei der Algorithmenkonfiguration von maschinellen Lernverfahren.
2018, M.Sc. thesis
[BibTeX]@mastersthesis { Land/2018,
title = {Ablaufplanungsverfahren zur effizienten Ressourcennutzung bei der Algorithmenkonfiguration von maschinellen Lernverfahren},
author = {Lang, Andreas},
school = {TU Dortmund},
year = {2018},
confidential = {n},
}
- Niklas Ueter:
Reservation-Based Federated Scheduling for Parallel Real-Time Tasks.
2018, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dipl. Inf. Georg von der Brüggen
[BibTeX]@mastersthesis { Ueter:2018,
title = {Reservation-Based Federated Scheduling for Parallel Real-Time Tasks},
author = {Ueter, Niklas},
school = {TU Dortmund},
year = {2018},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen and Dipl. Inf. Georg von der Br\"uggen},
}
- Nils Hölscher:
Nested Preemption Fixed-Priority Scheduler for EV3OSEK.
2018, B.Sc. thesis, Adviser: Kuan-Hsun Chen
[BibTeX][Abstract]@bachelorthesis { HoelscherBA,
title = {Nested Preemption Fixed-Priority Scheduler for EV3OSEK},
author = {H\"olscher, Nils},
school = {TU Dortmund},
year = {2018},
keywords = {Real-Time Operating System},
confidential = {n},
abstract = {Lego Mindstorms Robots are a popular platform for graduate level researches and college education purposes. As a portation of nxtOSEK, an OSEK standard compatible real-time operation system, EV3OSEK inherits the advantages of nxtOSEK for experiments on EV3, the latest generation of Mindstorms robots. Unfortunately, the current version of EV3OSEK still has some critical issues. In this work I address, task preemption, a common feature desired in every RTOS. Before relevant ARM specifications, parts of the OSEK standard and the historical background of EV3OSEK with nxtOSEK are explained. With this I reveal the related issues in the current design and propose corresponding solutions
for EV3OSEK that fix the issues in the IRQ-Handler and the task dispatching properly, thus enabling real multi-tasking on EV3OSEK. My evaluations show that the current design flaws are solved. Along with this work, I checked the current usability of EV3OSEK and suggest some future work to enhance EV3OSEK further, to make it a competitive alternative to other OS’s for the EV3 devices. },
adviser = {Kuan-Hsun Chen},
}
Lego Mindstorms Robots are a popular platform for graduate level researches and college education purposes. As a portation of nxtOSEK, an OSEK standard compatible real-time operation system, EV3OSEK inherits the advantages of nxtOSEK for experiments on EV3, the latest generation of Mindstorms robots. Unfortunately, the current version of EV3OSEK still has some critical issues. In this work I address, task preemption, a common feature desired in every RTOS. Before relevant ARM specifications, parts of the OSEK standard and the historical background of EV3OSEK with nxtOSEK are explained. With this I reveal the related issues in the current design and propose corresponding solutions
for EV3OSEK that fix the issues in the IRQ-Handler and the task dispatching properly, thus enabling real multi-tasking on EV3OSEK. My evaluations show that the current design flaws are solved. Along with this work, I checked the current usability of EV3OSEK and suggest some future work to enhance EV3OSEK further, to make it a competitive alternative to other OS’s for the EV3 devices.
- Juri Wenner:
Qualitätsoptimierung für digitale Bildverarbeitungsaufgaben in eingebetteten Systemen.
2018, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr.-Ing. Anas Toma
[BibTeX]@bachelorthesis { Wenner:2018,
title = {Qualit\"atsoptimierung f\"ur digitale Bildverarbeitungsaufgaben in eingebetteten Systemen},
author = {Wenner, Juri},
school = {TU Dortmund},
year = {2018},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen and Dr.-Ing. Anas Toma},
}
- Patrick Trockel:
Recognition of Attackers in the Context of Honeypots.
2018, M.Sc. thesis, Adviser: Prof. Dr. Peter Martini and Prof. Dr. Jian-Jia Chen
[BibTeX][Abstract]@mastersthesis { Trockel:2018,
title = {Recognition of Attackers in the Context of Honeypots},
author = {Trockel, Patrick},
school = {TU Dortmund},
year = {2018},
confidential = {n},
abstract = {According to the definition of a honeypot, any connection to or from this resource can
be considered as malicious and therefore as an attack. After detection, in particular, the
recognition of attackers or targeted attacks is a serious problem: Several sessions of pos-
sibly multiple attackers must be linked reliably.
For this purpose, an approach for targeted attacks is presented in this thesis which uses a
transparent proxy and a high-interaction honeypot as a foundation. These are integrated
into a complex architecture and allow an attacker to reach an isolated network segment
- the HoneyLab. Apart from the architecture active and passive measures are used to
recognize the attacker. Some of these include injection of unique credentials and URLs,
client and browser fingerprinting and a comprehensive data recording.
The main concept is to let the attacker build up a unique and compromised knowledge. If
the attacker uses this knowledge in several attacks or sessions, it will be used against him
which leads to recognition.
The implemented approach is evaluated with security professionals and random real-world
attackers. The security professionals were asked to behave as if they were participating
in a Capture the Flag (CTF) event and were reliably recognized by the approach. The
random real-world attackers could be detected but not recognized because they only used
automatic scans without any human interaction or malicious activities. Since targeted
attacks and not automatic scanners were focused, this can nevertheless be considered a
success.
},
adviser = {Prof. Dr. Peter Martini and Prof. Dr. Jian-Jia Chen},
}
According to the definition of a honeypot, any connection to or from this resource can
be considered as malicious and therefore as an attack. After detection, in particular, the
recognition of attackers or targeted attacks is a serious problem: Several sessions of pos-
sibly multiple attackers must be linked reliably.
For this purpose, an approach for targeted attacks is presented in this thesis which uses a
transparent proxy and a high-interaction honeypot as a foundation. These are integrated
into a complex architecture and allow an attacker to reach an isolated network segment
- the HoneyLab. Apart from the architecture active and passive measures are used to
recognize the attacker. Some of these include injection of unique credentials and URLs,
client and browser fingerprinting and a comprehensive data recording.
The main concept is to let the attacker build up a unique and compromised knowledge. If
the attacker uses this knowledge in several attacks or sessions, it will be used against him
which leads to recognition.
The implemented approach is evaluated with security professionals and random real-world
attackers. The security professionals were asked to behave as if they were participating
in a Capture the Flag (CTF) event and were reliably recognized by the approach. The
random real-world attackers could be detected but not recognized because they only used
automatic scans without any human interaction or malicious activities. Since targeted
attacks and not automatic scanners were focused, this can nevertheless be considered a
success.
- Siddharth Chithadka:
A PLC based real time material flow controller/calculator in warehouse management system.
2018, M.Sc. thesis, Adviser: Prof. Dr-Ing. Bernd Noche and Prof. Dr. Jian Jia Chen and M.Sc Cyril Alias
[BibTeX][Abstract]@mastersthesis { Chithadka:2018,
title = {A PLC based real time material flow controller/calculator in warehouse management system},
author = {Chithadka, Siddharth},
school = {TU Dortmund},
year = {2018},
confidential = {n},
abstract = {The thesis involves developing the software architecture for material flow cal-
culator (Material Fluss Rechner: MFR) in small warehouse systems, which
not only helps in automating the process in semi automated or manual ware-
house conveyor line, but also increases the productivity of the same by auto-
matically scanning and updating the database. It further leads to systematic
representation of data in a warehouse thereby reducing the error in various
stages of material in warehouse and eventually reducing the turnaround time.
The proposed software model and architecture guides the material on con-
veyor line to the required destination in warehouse and it updates the datalog
file cyclically. The main emphasis on developing the Material flow calcula-
tor software model is laid on the algorithm which guides the material to the
required destination as early as possible by combining the ideas from vari-
ous optimisation algorithms like Improved Djikstra’s method and Disjunctive
Branch and Bound. Furthermore a brief working algorithm model to syn-
chronise the material flow with the database is also developed. In this thesis
work we propose a routing algorithm by modelling the material flow as a job
shop problem considering all the constraints and by having makespan as an
objective function. The above proposed heuristic algorithm tends to counter
problems seen like blocking or deadlocks and schedules the flow of material
in a optimised manner on a conveyor line. In order to quantify the algorithm
the logic is written in a PLC programming language (IEC 61131-3), similar
to ANSI C language which is realised through B\&R Automation Studio soft-
ware ® and the data during material flow is recorded by a Bar code reader
which is later synchronized cyclically with the SQL server database. To val-
idate the algorithm, the proposed software model was simulated on a B\&R
PLC PC 2100, which identified MFR’s performance under various scenarios.
},
adviser = {Prof. Dr-Ing. Bernd Noche and Prof. Dr. Jian Jia Chen and M.Sc Cyril Alias},
}
The thesis involves developing the software architecture for material flow cal-
culator (Material Fluss Rechner: MFR) in small warehouse systems, which
not only helps in automating the process in semi automated or manual ware-
house conveyor line, but also increases the productivity of the same by auto-
matically scanning and updating the database. It further leads to systematic
representation of data in a warehouse thereby reducing the error in various
stages of material in warehouse and eventually reducing the turnaround time.
The proposed software model and architecture guides the material on con-
veyor line to the required destination in warehouse and it updates the datalog
file cyclically. The main emphasis on developing the Material flow calcula-
tor software model is laid on the algorithm which guides the material to the
required destination as early as possible by combining the ideas from vari-
ous optimisation algorithms like Improved Djikstra’s method and Disjunctive
Branch and Bound. Furthermore a brief working algorithm model to syn-
chronise the material flow with the database is also developed. In this thesis
work we propose a routing algorithm by modelling the material flow as a job
shop problem considering all the constraints and by having makespan as an
objective function. The above proposed heuristic algorithm tends to counter
problems seen like blocking or deadlocks and schedules the flow of material
in a optimised manner on a conveyor line. In order to quantify the algorithm
the logic is written in a PLC programming language (IEC 61131-3), similar
to ANSI C language which is realised through B&R Automation Studio soft-
ware ® and the data during material flow is recorded by a Bar code reader
which is later synchronized cyclically with the SQL server database. To val-
idate the algorithm, the proposed software model was simulated on a B&R
PLC PC 2100, which identified MFR’s performance under various scenarios.
- Nils Hölscher:
Nested Preemption Fixed-Priority Scheduler for EV3OSEK.
2018, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Kuan-Hsun Chen
[BibTeX][Abstract]@bachelorthesis { Hoelscher:2018,
title = {Nested Preemption Fixed-Priority Scheduler for EV3OSEK},
author = {H\"olscher, Nils},
school = {TU Dortmund},
year = {2018},
confidential = {n},
abstract = {Lego Mindstorms Robots are a popular platform for graduate level researches and college education purposes. As a portation of nxtOSEK, an OSEK standard compatible real-time operation system, EV3OSEK inherits the advantages of nxtOSEK for experiments on EV3, the latest generation of Mindstorms robots. Unfortunately, the current version of EV3OSEK still has some critical issues. In this work I address task preemption, a common feature desired in every RTOS. But before relevant ARM specifications, parts of the OSEK standard and the historical background of EV3OSEK with nxtOSEK are explained. With this I reveal the related issues in the current design and propose corresponding solutions for EV3OSEK that fix the issues in the IRQ-Handler and the task dispatching properly, thus enabling real multi-tasking on EV3OSEK. My evaluations show that the current design flaws are solved. Along with this work, I checked the current usability of EV3OSEK and proposed some future work to enhance EV3OSEK further, to make it an alternative to
other OS’s for the EV3 devices. },
adviser = {Prof. Dr. Jian-Jia Chen and Kuan-Hsun Chen},
}
Lego Mindstorms Robots are a popular platform for graduate level researches and college education purposes. As a portation of nxtOSEK, an OSEK standard compatible real-time operation system, EV3OSEK inherits the advantages of nxtOSEK for experiments on EV3, the latest generation of Mindstorms robots. Unfortunately, the current version of EV3OSEK still has some critical issues. In this work I address task preemption, a common feature desired in every RTOS. But before relevant ARM specifications, parts of the OSEK standard and the historical background of EV3OSEK with nxtOSEK are explained. With this I reveal the related issues in the current design and propose corresponding solutions for EV3OSEK that fix the issues in the IRQ-Handler and the task dispatching properly, thus enabling real multi-tasking on EV3OSEK. My evaluations show that the current design flaws are solved. Along with this work, I checked the current usability of EV3OSEK and proposed some future work to enhance EV3OSEK further, to make it an alternative to
other OS’s for the EV3 devices.
- Rajith Hebbal Ravikumar:
Improvement of Vehicle Motion Information by Visual Odometry.
2018, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr. Holger Faisst
[BibTeX][Abstract]@mastersthesis { Ravikumar:2018,
title = {Improvement of Vehicle Motion Information by Visual Odometry},
author = {Ravikumar, Rajith Hebbal},
school = {TU Dortmund},
year = {2018},
confidential = {n},
abstract = {A driver-less vehicle and Vehicle-to-Anything (V2X) systems highly rely on accurate and
reliable motion information of the vehicle when it travels around the surrounding (inside
and outside) environment. As a consequence, it is essential to maintain the precise vehi-
cle’s information such as pose of the vehicle (position and direction) for its navigation.
Further, the most important dispute in autonomous application is to obtain good estima-
tion of position and orientation values for improving its performance. For accomplishing
this, the conventional localization approach seen in [1] use the measurements from Global
Navigation Satellite System (GNSS) and Inertial measurement unit (IMU).
The major drawback of that conventional approach is :
1 The errors will get accumulated over the time because of the drift present in the
IMU measurement data, and
2 The signal from GNSS will not be fully available or not reliable i.e. sometime the
strength of the GNSS signal will be diminished in some region, for instance, in
dense urban city, inside the tunnel, etc.
Thereby, it is very difficult to get good estimation of localization information from those
sensor measurements.
In this thesis work, we propose a stereo-vision based vehicle localization method to over-
come the drawback of above mentioned traditional approach. In the proposed method,
we use visual odometry technique [2] together with IMU, GNSS, and wheel odometry for
estimating the pose of the vehicle in GPS denied environment. The measurement data
from multiple sensors are fused together using Extended Kalman Filter(EKF) approach
[3][4] to provide more accurate and reliable motion information for autonomous vehicle
navigation. The proposed method can perform with, or independently of GNSS system,
thereby it can be used as a backup to GNSS system. And also we have tested the developed algorithm on both simulated and real data.
},
adviser = {Prof. Dr. Jian-Jia Chen and Dr. Holger Faisst},
}
A driver-less vehicle and Vehicle-to-Anything (V2X) systems highly rely on accurate and
reliable motion information of the vehicle when it travels around the surrounding (inside
and outside) environment. As a consequence, it is essential to maintain the precise vehi-
cle’s information such as pose of the vehicle (position and direction) for its navigation.
Further, the most important dispute in autonomous application is to obtain good estima-
tion of position and orientation values for improving its performance. For accomplishing
this, the conventional localization approach seen in [1] use the measurements from Global
Navigation Satellite System (GNSS) and Inertial measurement unit (IMU).
The major drawback of that conventional approach is :
1 The errors will get accumulated over the time because of the drift present in the
IMU measurement data, and
2 The signal from GNSS will not be fully available or not reliable i.e. sometime the
strength of the GNSS signal will be diminished in some region, for instance, in
dense urban city, inside the tunnel, etc.
Thereby, it is very difficult to get good estimation of localization information from those
sensor measurements.
In this thesis work, we propose a stereo-vision based vehicle localization method to over-
come the drawback of above mentioned traditional approach. In the proposed method,
we use visual odometry technique [2] together with IMU, GNSS, and wheel odometry for
estimating the pose of the vehicle in GPS denied environment. The measurement data
from multiple sensors are fused together using Extended Kalman Filter(EKF) approach
[3][4] to provide more accurate and reliable motion information for autonomous vehicle
navigation. The proposed method can perform with, or independently of GNSS system,
thereby it can be used as a backup to GNSS system. And also we have tested the developed algorithm on both simulated and real data.
- Olaf Neugebauer:
Efficient Implementation of Resource-Constrained Cyber-Physical Systems using Multi-Core Parallelism.
2018, PhD thesis
[BibTeX][Link]@phdthesis { neugebauer/2018,
title = {Efficient Implementation of Resource-Constrained Cyber-Physical Systems using Multi-Core Parallelism},
author = {Neugebauer, Olaf},
school = {TU Dortmund},
year = {2018},
url = {http://dx.doi.org/10.17877/DE290R-18927},
confidential = {n},
}
- Shabnam Tabatabaian:
Real-Time Synchronization on Multiprocessors through Suspension or Spinning?.
2018, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dipl.-Inf. Georg von der Brüggen
[BibTeX][Abstract]@mastersthesis { Tabatabaian:2018,
title = {Real-Time Synchronization on Multiprocessors through Suspension or Spinning?},
author = {Tabatabaian, Shabnam},
school = {TU Dortmund},
year = {2018},
confidential = {n},
abstract = {For many real-time applications, it is often too restrictive to assume that tasks are executed only
in a uniprocessor system and all of them are completely independent, because tasks will often
compete for shared resources. The access to the shared resource, called critical section of the task
execution, is mutually exclusive to prevent race conditions. In fact, it is not possible that two jobs
access the shared resource at the same time. As shared resources must be serially executed to
achieve mutual exclusion, the execution of critical sections inevitably causes some delay due to
priority inversion, which means, a task is prevented from executing due to another task with a
lower priority that holds a shared resource, also called pi-blocking. To avoid unnecessary blocking
of high-priority tasks due to unrelated shared resources, there exists some locking protocols. Two
well-known of these locking protocols for systems with one processor, also called uniprocessor
systems, are Priority Inheritance Protocol (PIP) [1] and the Priority Ceiling Protocol (PCP) [1].
Although the PIP could solve the problem of priority inversion, it might cause a deadlock if there
are multiple resources. Through the use of PCP proposed by Sha et. al [1], deadlock can never
occur.
Resource sharing becomes more complex when considering multiprocessor platforms instead of
uniprocessor platforms, because in multiprocessor systems the task-suspending and task-spinning
may come into play. Under spinning approach, tasks busy-wait in a tight loop or called “spin” to
the processor, while it is waiting for accessing a shared resource. Under suspending approach,
tasks relinquish their processor and suspend during the time waiting for a shared resource
accessing. There exist some protocols, which support both mechanisms, e.g. Multiprocessor Slack
Resource Policy (MSRP) [2] as a spin-based multiprocessor locking protocol as well as Distributed
Priority Ceiling Protocol (DPCP) [3] and Multiprocessor Priority Ceiling Protocol (MPCP) [4]
under suspending approach. Although, many suspension-based and spin-based locking protocols
have been designed and analyzed in the last years, it has been relatively little investigated, that
under which settings which one of the suspension-based and the spin-based locking protocols are
in general preferable. Therefore, this tradeoff has to be analyzed and some break-even
configurations should be determined. The only result in this area is published in [5], which
concludes that “blocking by suspending is rarely preferable to spinning (provided spinning can be
done in-cache, which we assume)”. However, the analysis in [5] is conducted only considering the
Flexible Multiprocessor Locking Protocol (FMLP).
In this thesis other locking protocols than FMLP will be taken into consideration and finally the
conditions that favor spin-based locking protocols over suspension-based locking protocols and
the other way around, will be specified. To this end, first a test-bed based on the platform
LITMUSRT [6] [7] will be set up and then those protocols will be tested under different settings of
properties such as number of processors, number of resource accesses per task, period of each task
and etc. to find the break-even configurations.
},
adviser = {Prof. Dr. Jian-Jia Chen and Dipl.-Inf. Georg von der Br\"uggen},
}
For many real-time applications, it is often too restrictive to assume that tasks are executed only
in a uniprocessor system and all of them are completely independent, because tasks will often
compete for shared resources. The access to the shared resource, called critical section of the task
execution, is mutually exclusive to prevent race conditions. In fact, it is not possible that two jobs
access the shared resource at the same time. As shared resources must be serially executed to
achieve mutual exclusion, the execution of critical sections inevitably causes some delay due to
priority inversion, which means, a task is prevented from executing due to another task with a
lower priority that holds a shared resource, also called pi-blocking. To avoid unnecessary blocking
of high-priority tasks due to unrelated shared resources, there exists some locking protocols. Two
well-known of these locking protocols for systems with one processor, also called uniprocessor
systems, are Priority Inheritance Protocol (PIP) [1] and the Priority Ceiling Protocol (PCP) [1].
Although the PIP could solve the problem of priority inversion, it might cause a deadlock if there
are multiple resources. Through the use of PCP proposed by Sha et. al [1], deadlock can never
occur.
Resource sharing becomes more complex when considering multiprocessor platforms instead of
uniprocessor platforms, because in multiprocessor systems the task-suspending and task-spinning
may come into play. Under spinning approach, tasks busy-wait in a tight loop or called “spin” to
the processor, while it is waiting for accessing a shared resource. Under suspending approach,
tasks relinquish their processor and suspend during the time waiting for a shared resource
accessing. There exist some protocols, which support both mechanisms, e.g. Multiprocessor Slack
Resource Policy (MSRP) [2] as a spin-based multiprocessor locking protocol as well as Distributed
Priority Ceiling Protocol (DPCP) [3] and Multiprocessor Priority Ceiling Protocol (MPCP) [4]
under suspending approach. Although, many suspension-based and spin-based locking protocols
have been designed and analyzed in the last years, it has been relatively little investigated, that
under which settings which one of the suspension-based and the spin-based locking protocols are
in general preferable. Therefore, this tradeoff has to be analyzed and some break-even
configurations should be determined. The only result in this area is published in [5], which
concludes that “blocking by suspending is rarely preferable to spinning (provided spinning can be
done in-cache, which we assume)”. However, the analysis in [5] is conducted only considering the
Flexible Multiprocessor Locking Protocol (FMLP).
In this thesis other locking protocols than FMLP will be taken into consideration and finally the
conditions that favor spin-based locking protocols over suspension-based locking protocols and
the other way around, will be specified. To this end, first a test-bed based on the platform
LITMUSRT [6] [7] will be set up and then those protocols will be tested under different settings of
properties such as number of processors, number of resource accesses per task, period of each task
and etc. to find the break-even configurations.
- Helena Kotthaus:
Methods for Efficient Resource Utilization in Statistical Machine Learning Algorithms.
Department of Computer Science XII, TU Dortmund University, June 2018, PhD thesis, Adviser: Prof. Dr. Peter Marwedel
[BibTeX][Link][Abstract]@phdthesis { kotthaus/2018b,
title = {Methods for Efficient Resource Utilization in Statistical Machine Learning Algorithms},
author = {Kotthaus, Helena},
school = {TU Dortmund University},
year = {2018},
address = {Department of Computer Science XII, TU Dortmund University},
month = {June},
url = {https://eldorado.tu-dortmund.de/bitstream/2003/36929/1/Dissertation_Kotthaus.pdf},
confidential = {n},
abstract = {In recent years, statistical machine learning has emerged as a key technique for tackling problems that elude a classic algorithmic approach. One such problem, with a major impact on human life, is the analysis of complex biomedical data. Solving this problem in a fast and efficient manner is of major importance, as it enables, e.g., the prediction of the efficacy of different drugs for therapy selection. While achieving the highest possible prediction quality appears desirable, doing so is often simply infeasible due to resource constraints. Statistical learning algorithms for predicting the health status of a patient or for finding the best algorithm configuration for the prediction require an excessively high amount of resources. Furthermore, these algorithms are often implemented with no awareness of the underlying system architecture, which leads to sub-optimal resource utilization. This thesis presents methods for efficient resource utilization of statistical learning applications. The goal is to reduce the resource demands of these algorithms to meet a given time budget while simultaneously preserving the prediction quality. As a first step, the resource consumption characteristics of learning algorithms are analyzed, as well as their scheduling on underlying parallel architectures, in order to develop optimizations that enable these algorithms to scale to larger problem sizes. For this purpose, new profiling mechanisms are incorporated into a holistic profiling framework. The results show that one major contributor to the resource issues is memory consumption. To overcome this obstacle, a new optimization based on dynamic sharing of memory is developed that speeds up computation by several orders of magnitude in situations when available main memory is the bottleneck, leading to swapping out memory. One important application that can be applied for automated parameter tuning of learning algorithms is model-based optimization. Within a huge search space, algorithm configurations are evaluated to find the configuration with the best prediction quality. An important step towards better managing this search space is to parallelize the search process itself. However, a high runtime variance within the configuration space can cause inefficient resource utilization. For this purpose, new resource-aware scheduling strategies are developed that efficiently map evaluations of configurations to the parallel architecture, depending on their resource demands. In contrast to classical scheduling problems, the new scheduling interacts with the configuration proposal mechanism to select configurations with suitable resource demands. With these strategies, it becomes possible to make use of the full potential of parallel architectures. Compared to established parallel execution models, the results show that the new approach enables model-based optimization to converge faster to the optimum within a given time budget.},
adviser = {Prof. Dr. Peter Marwedel},
}
In recent years, statistical machine learning has emerged as a key technique for tackling problems that elude a classic algorithmic approach. One such problem, with a major impact on human life, is the analysis of complex biomedical data. Solving this problem in a fast and efficient manner is of major importance, as it enables, e.g., the prediction of the efficacy of different drugs for therapy selection. While achieving the highest possible prediction quality appears desirable, doing so is often simply infeasible due to resource constraints. Statistical learning algorithms for predicting the health status of a patient or for finding the best algorithm configuration for the prediction require an excessively high amount of resources. Furthermore, these algorithms are often implemented with no awareness of the underlying system architecture, which leads to sub-optimal resource utilization. This thesis presents methods for efficient resource utilization of statistical learning applications. The goal is to reduce the resource demands of these algorithms to meet a given time budget while simultaneously preserving the prediction quality. As a first step, the resource consumption characteristics of learning algorithms are analyzed, as well as their scheduling on underlying parallel architectures, in order to develop optimizations that enable these algorithms to scale to larger problem sizes. For this purpose, new profiling mechanisms are incorporated into a holistic profiling framework. The results show that one major contributor to the resource issues is memory consumption. To overcome this obstacle, a new optimization based on dynamic sharing of memory is developed that speeds up computation by several orders of magnitude in situations when available main memory is the bottleneck, leading to swapping out memory. One important application that can be applied for automated parameter tuning of learning algorithms is model-based optimization. Within a huge search space, algorithm configurations are evaluated to find the configuration with the best prediction quality. An important step towards better managing this search space is to parallelize the search process itself. However, a high runtime variance within the configuration space can cause inefficient resource utilization. For this purpose, new resource-aware scheduling strategies are developed that efficiently map evaluations of configurations to the parallel architecture, depending on their resource demands. In contrast to classical scheduling problems, the new scheduling interacts with the configuration proposal mechanism to select configurations with suitable resource demands. With these strategies, it becomes possible to make use of the full potential of parallel architectures. Compared to established parallel execution models, the results show that the new approach enables model-based optimization to converge faster to the optimum within a given time budget.
- Filip Chocholak:
Usefulness of Model-Based Testing Within Simulink Platform.
March 2018, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr. Stefan Schneider
[BibTeX][Abstract]@mastersthesis { Chocholak:2018,
title = {Usefulness of Model-Based Testing Within Simulink Platform},
author = {Chocholak, Filip},
school = {TU Dortmund},
year = {2018},
month = {March},
confidential = {n},
abstract = {The trends of drastic increase of software features in relation to popular electric and self-
driving cars pushes the industry to think more vast. To think more software features
in vehicles, require more attention, towards safety and high product quality error-free
aspects. To ensure such manners, more effort regarding testing must be considered. To
test as early as possible, starting from the component Level through the integration Level
up to the system Level while performing Model-Based Development (MBD). One of the
approaches that has gained attention in the context of the Model-Based Development is
the Model-Based Testing (MBT).
In this Thesis, an overview of the usefulness of Model-Based Testing within a standard
Model-Based Development platform Simulink for automotive applications will be intro-
duced. Firstly, a detailed investigation regarding MBT approaches covering functional
perspective will be performed by exploring two MBT tools: the Simulink Design Verifier
from Mathworks Inc. and the TPT from PikeTec GmbH. The objectives are to look deeply
inside of the MBT methods used for each tool by analyzing the modeling, execution and
evaluation of the test cases from the different system levels as well as from the different
requirement categories points of view. For these reasons, the categorization of require-
ments based on the concurrent level of the system as well as based on its characteristics
have to be established. Moreover, based on these investigations, conclusions regarding
the testing activities performing at various system level will be conducted. Secondly, the
analysis based on the model complexity, scalability and applicability for each tool will be
performed.
To fulfill these objectives a case study model was selected. The model introduced basic
functionality for Power Window Control System in vehicles modeled using Simulink Func-
tional Block Diagrams. Due to the simplicity of the case study model, the results are
limited with respect to its applicability.
},
adviser = {Prof. Dr. Jian-Jia Chen and Dr. Stefan Schneider},
}
The trends of drastic increase of software features in relation to popular electric and self-
driving cars pushes the industry to think more vast. To think more software features
in vehicles, require more attention, towards safety and high product quality error-free
aspects. To ensure such manners, more effort regarding testing must be considered. To
test as early as possible, starting from the component Level through the integration Level
up to the system Level while performing Model-Based Development (MBD). One of the
approaches that has gained attention in the context of the Model-Based Development is
the Model-Based Testing (MBT).
In this Thesis, an overview of the usefulness of Model-Based Testing within a standard
Model-Based Development platform Simulink for automotive applications will be intro-
duced. Firstly, a detailed investigation regarding MBT approaches covering functional
perspective will be performed by exploring two MBT tools: the Simulink Design Verifier
from Mathworks Inc. and the TPT from PikeTec GmbH. The objectives are to look deeply
inside of the MBT methods used for each tool by analyzing the modeling, execution and
evaluation of the test cases from the different system levels as well as from the different
requirement categories points of view. For these reasons, the categorization of require-
ments based on the concurrent level of the system as well as based on its characteristics
have to be established. Moreover, based on these investigations, conclusions regarding
the testing activities performing at various system level will be conducted. Secondly, the
analysis based on the model complexity, scalability and applicability for each tool will be
performed.
To fulfill these objectives a case study model was selected. The model introduced basic
functionality for Power Window Control System in vehicles modeled using Simulink Func-
tional Block Diagrams. Due to the simplicity of the case study model, the results are
limited with respect to its applicability.
- Timo Gojowczyk:
Efficient Timer Mechanism in Real Time Operating Systems.
January 2018, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, M.Sc. Kuan-Hsun Chen
[BibTeX]@bachelorthesis { Timo:2018,
title = {Efficient Timer Mechanism in Real Time Operating Systems},
author = {Gojowczyk, Timo},
school = {TU Dortmund},
year = {2018},
month = {January},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, M.Sc. Kuan-Hsun Chen},
}
2017
- Marco Dürr:
Analysis and Optimisation of Signal-Flows in Real-Time Embedded Parallel Software Applications.
2017, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr. Matthias Freier
[BibTeX][Abstract]@mastersthesis { Dürr:2017,
title = {Analysis and Optimisation of Signal-Flows in Real-Time Embedded Parallel Software Applications},
author = {D\"urr, Marco},
school = {TU Dortmund},
year = {2017},
confidential = {n},
abstract = {Over the last decades, the real-time system community has developed useful approaches for timing and scheduling analysis of different processor types and buses. These days, more in-depth topics like end-to-end timing gain in importance. The purpose of this thesis is to present a workflow to determine important end-to-end paths (signal-flows) and to analyse them with respect to their timing behaviour. Therefore, fundamental concepts of graph theory and real-time systems are used to develop specific end-to-end timing models that are general applicable
to industrial software applications. Furthermore, different communication and response time semantics are investigated, which are required to obtain a tight end-to-end timing analysis for signal-flows. The evaluation of the influence of an increasing system utilisation to the response time of a signal-flow shows the importance to distinguish between the various semantics. },
adviser = {Prof. Dr. Jian-Jia Chen and Dr. Matthias Freier},
}
Over the last decades, the real-time system community has developed useful approaches for timing and scheduling analysis of different processor types and buses. These days, more in-depth topics like end-to-end timing gain in importance. The purpose of this thesis is to present a workflow to determine important end-to-end paths (signal-flows) and to analyse them with respect to their timing behaviour. Therefore, fundamental concepts of graph theory and real-time systems are used to develop specific end-to-end timing models that are general applicable
to industrial software applications. Furthermore, different communication and response time semantics are investigated, which are required to obtain a tight end-to-end timing analysis for signal-flows. The evaluation of the influence of an increasing system utilisation to the response time of a signal-flow shows the importance to distinguish between the various semantics.
- Abubakar Sanaullah:
Model based Tolerance and Error Analysis of Inertial Sensor based Measurement System of an Excavator.
2017, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr.-Ing. Philip Nagel
[BibTeX][Abstract]@mastersthesis { Sanaullah:2017,
title = {Model based Tolerance and Error Analysis of Inertial Sensor based Measurement System of an Excavator},
author = {Sanaullah, Abubakar},
school = {TU Dortmund},
year = {2017},
confidential = {n},
abstract = {The thesis investigates the applicability of the current state of art in mobile excavators to semi-automate the digging function which not only helps the operator in controlling the tool inclination but also adds to the safety and reduces work load. The developed model estimates the position of an end-effector of an excavator with certain accuracy, having limited or no information about the critical system parameters that contribute to the estimation error. In this study, various sources of error such as sensor errors, calibration errors and mechanical/geometric errors are identified. Analytical models are derived for the selected parameters and their inclusion to the existing process is shown. In order to quantify the impact of each parameter on system accuracy, a detailed error analysis is performed. Two test cases are studied, and the error is recorded for the typical and maximum variations in each case. A variance based global sensitivity analysis method is employed to measure not only the main effect of a parameter but all the interactions in the model involving that parameter. The variations in parameters are represented by probability distributions and error is propagated using Monte Carlo simulations. The parameters are then ranked based on their contribution to the total output variance. Although it depends on test cases, filters used for estimation and parameter tolerances; the results of both individual error analysis and Sobol analysis have illustrated that sensitive parameters remained the same.
},
adviser = {Prof. Dr. Jian-Jia Chen and Dr.-Ing. Philip Nagel},
}
The thesis investigates the applicability of the current state of art in mobile excavators to semi-automate the digging function which not only helps the operator in controlling the tool inclination but also adds to the safety and reduces work load. The developed model estimates the position of an end-effector of an excavator with certain accuracy, having limited or no information about the critical system parameters that contribute to the estimation error. In this study, various sources of error such as sensor errors, calibration errors and mechanical/geometric errors are identified. Analytical models are derived for the selected parameters and their inclusion to the existing process is shown. In order to quantify the impact of each parameter on system accuracy, a detailed error analysis is performed. Two test cases are studied, and the error is recorded for the typical and maximum variations in each case. A variance based global sensitivity analysis method is employed to measure not only the main effect of a parameter but all the interactions in the model involving that parameter. The variations in parameters are represented by probability distributions and error is propagated using Monte Carlo simulations. The parameters are then ranked based on their contribution to the total output variance. Although it depends on test cases, filters used for estimation and parameter tolerances; the results of both individual error analysis and Sobol analysis have illustrated that sensitive parameters remained the same.
- Rico Endern:
Power Management in heterogenen Multiprocessing-Systemen.
August 2017, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr. Anas Toma
[BibTeX]@bachelorthesis { Rico:2017,
title = {Power Management in heterogenen Multiprocessing-Systemen},
author = {Endern, Rico},
year = {2017},
month = {August},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen and Dr. Anas Toma},
}
- Alexander Starinow:
Saving Energy in Embedded Systems Using Nearby Resources.
August 2017, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr. Anas Toma
[BibTeX][Abstract]@bachelorthesis { Alexander:2017,
title = {Saving Energy in Embedded Systems Using Nearby Resources},
author = {Starinow, Alexander},
year = {2017},
month = {August},
confidential = {n},
abstract = {This thesis evaluates the energy consumption of a device that executes tasks locally and uses auxiliary resources. Mobile embedded systems are widespread in today’s society and are used for all kinds of purposes whatsoever. However, these embedded systems have limitations with respect to processing power and battery life, due to the requirement of being mobile. To overcome these limitations these systems communicate with servers to save energy and increase computation speed. In the setup in this thesis, the remote execution of a task on a server can theoretically reduce the consumption of energy by 99%.
But there are some challenges when communicating with a server. A network can be overloaded and therefore have a low bandwidth or being not reachable. This thesis proposes a new model that uses Nearby Resources as Auxiliary Resources. This model will be evaluated on real hardware using different tasks as examples for real-life applications. Using Nearby Resources can save up to 98% per task and also reduce the workload on remote servers and the relieve the bandwidth.},
adviser = {Prof. Dr. Jian-Jia Chen and Dr. Anas Toma},
}
This thesis evaluates the energy consumption of a device that executes tasks locally and uses auxiliary resources. Mobile embedded systems are widespread in today’s society and are used for all kinds of purposes whatsoever. However, these embedded systems have limitations with respect to processing power and battery life, due to the requirement of being mobile. To overcome these limitations these systems communicate with servers to save energy and increase computation speed. In the setup in this thesis, the remote execution of a task on a server can theoretically reduce the consumption of energy by 99%.
But there are some challenges when communicating with a server. A network can be overloaded and therefore have a low bandwidth or being not reachable. This thesis proposes a new model that uses Nearby Resources as Auxiliary Resources. This model will be evaluated on real hardware using different tasks as examples for real-life applications. Using Nearby Resources can save up to 98% per task and also reduce the workload on remote servers and the relieve the bandwidth.
- Nadzeya Liabiodka:
Analyzing and evaluating resource synchronization protocols in RTEMS on multi-core systems.
June 2017, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, M.Sc. Kuan-Hsun Chen
[BibTeX]@bachelorthesis { Liabiodka:2017,
title = {Analyzing and evaluating resource synchronization protocols in RTEMS on multi-core systems},
author = {Liabiodka, Nadzeya},
school = {TU Dortmund},
year = {2017},
month = {June},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, M.Sc. Kuan-Hsun Chen},
}
- Lea Schönberger:
Multicore Systems with Dynamic Real-Time Guarantees.
May 2017, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, Dipl.-Inf. Georg von der Brüggen
[BibTeX]@mastersthesis { schoenberger2017,
title = {Multicore Systems with Dynamic Real-Time Guarantees},
author = {Sch\"onberger, Lea},
school = {TU Dortmund},
year = {2017},
month = {May},
keywords = {lea},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, Dipl.-Inf. Georg von der Br\"uggen},
}
- Benjamin Gläser:
Resource-Aware Optimization by Trading Locality, Redundancy and Parallelism.
April 2017, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dipl.-Inf. Ingo Korb
[BibTeX][Abstract]@bachelorthesis { Glaeser:2017,
title = {Resource-Aware Optimization by Trading Locality, Redundancy and Parallelism},
author = {Gl\"aser, Benjamin},
year = {2017},
month = {April},
confidential = {n},
abstract = {This thesis analyses the possibility and shortcomings of automated resource-aware optimization by making use of locality, redundancy and parallelism. It is to be expected that different platforms and hardware will see benefits and drawbacks depending on the strategy used.
To study these effects further, a field of application is required, where the three aforementioned approaches can be utilized. Due to its nature and scalability, image processing represents an ideal candidate for this. The choice of image processing is the focus of this work, as it is also a domain that has been extensively researched and gaining importance in recent years.
Whilst most research on image processing acceleration mainly focuses on the ease of implementation and optimization for a specific platform, the thesis at hand aims to investigate the newest development in automatic resource-aware optimization.
This requires the identification of patterns and subsets within the possible hardware configurations and image processing pipelines that exhibit similar behavior, when faced with the challenge of trading locality, redundancy and parallelism. Using these characteristics as a basis, this thesis aims to study their effect on automatically generated schedules.},
adviser = {Prof. Dr. Jian-Jia Chen and Dipl.-Inf. Ingo Korb},
}
This thesis analyses the possibility and shortcomings of automated resource-aware optimization by making use of locality, redundancy and parallelism. It is to be expected that different platforms and hardware will see benefits and drawbacks depending on the strategy used.
To study these effects further, a field of application is required, where the three aforementioned approaches can be utilized. Due to its nature and scalability, image processing represents an ideal candidate for this. The choice of image processing is the focus of this work, as it is also a domain that has been extensively researched and gaining importance in recent years.
Whilst most research on image processing acceleration mainly focuses on the ease of implementation and optimization for a specific platform, the thesis at hand aims to investigate the newest development in automatic resource-aware optimization.
This requires the identification of patterns and subsets within the possible hardware configurations and image processing pipelines that exhibit similar behavior, when faced with the challenge of trading locality, redundancy and parallelism. Using these characteristics as a basis, this thesis aims to study their effect on automatically generated schedules.
- Osama Maqbool:
System Optimization of Hybrid Marine Systems.
April 2017, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr.-Ing. Philip Nagel
[BibTeX][Abstract]@mastersthesis { Maqbool:2017,
title = {System Optimization of Hybrid Marine Systems},
author = {Maqbool, Osama},
year = {2017},
month = {April},
confidential = {n},
abstract = {Dynamic Programming is a highly effective technique for the offline optimization of power trains, as it guarantees a globally optimal solution. This study investigates the two major problems associated with the application of dynamic programming for the optimization of hybrid marine power trains.
The first issue is the high number of computations, which increases exponentially with the size of the problem. In order to reduce the number of computations, a variant of dynamic programming is investigated, called the iterative dynamic programming. The implementation problems with iterative dynamic programming have also been investigated and solutions are proposed to tackle the problems.
The second issue is the loss of optimality due to the discretization of the continuous power train model. The introduction of different errors and their propagation through the optimization process is investigated. Multiple solutions are proposed in this area that aim to reduce the discretization errors without increasing the number of computations.
In order to test and experimentally verify the investigations, two test cases of hybrid power trains are defined. The regular dynamic programming algorithm, as well as the proposed methodologies for improving the performance of the algorithm are implemented and tested for the two test cases. The performance of the test cases for different algorithms is presented in a comparative fashion.},
adviser = {Prof. Dr. Jian-Jia Chen and Dr.-Ing. Philip Nagel},
}
Dynamic Programming is a highly effective technique for the offline optimization of power trains, as it guarantees a globally optimal solution. This study investigates the two major problems associated with the application of dynamic programming for the optimization of hybrid marine power trains.
The first issue is the high number of computations, which increases exponentially with the size of the problem. In order to reduce the number of computations, a variant of dynamic programming is investigated, called the iterative dynamic programming. The implementation problems with iterative dynamic programming have also been investigated and solutions are proposed to tackle the problems.
The second issue is the loss of optimality due to the discretization of the continuous power train model. The introduction of different errors and their propagation through the optimization process is investigated. Multiple solutions are proposed in this area that aim to reduce the discretization errors without increasing the number of computations.
In order to test and experimentally verify the investigations, two test cases of hybrid power trains are defined. The regular dynamic programming algorithm, as well as the proposed methodologies for improving the performance of the algorithm are implemented and tested for the two test cases. The performance of the test cases for different algorithms is presented in a comparative fashion.
- Vincent Meyers:
Evaluation of Multi-Mode Tasks under Rate-Monotonic and Earliest-Deadline-First Scheduling in Real-Time Systems.
April 2017, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen and Dr. Anas Toma
[BibTeX]@bachelorthesis { Vincent:2017,
title = {Evaluation of Multi-Mode Tasks under Rate-Monotonic and Earliest-Deadline-First Scheduling in Real-Time Systems},
author = {Meyers, Vincent},
year = {2017},
month = {April},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen and Dr. Anas Toma},
}
- Wen-Hung Huang:
Scheduling algorithms and timing analysis for hard real-time systems.
Dortmund, Germany, April 2017, PhD thesis, Adviser: Prof. Dr. Jian-Jia Chen , Examiner: Prof. Dr. Jan Reineke (Uni Saarland)
[BibTeX][PDF][Link][Abstract]@phdthesis { dissertation-Kevin-Huang-2017,
title = {Scheduling algorithms and timing analysis for hard real-time systems},
author = {Huang, Wen-Hung},
school = {TU Dortmund},
year = {2017},
type = {Dissertation},
address = {Dortmund, Germany},
month = {April},
url = {https://eldorado.tu-dortmund.de/bitstream/2003/35984/1/Dissertation_Huang_pdfa.pdf},
keywords = {Hartes Echtzeitsystem, Worst-Case-Laufzeit, Scheduling},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2017-Huang-Dissertation.pdf},
confidential = {n},
abstract = {Real-time systems are designed for applications in which response time is critical. As timing is a major property of such systems, proving timing correctness is of utter importance. To achieve this, a two-fold approach of timing analysis is traditionally involved: (i) worst-case execution time (WCET) analysis, which computes an upper bound on the execution time of a single job of a task running in isolation; and (ii) schedulability analysis using the WCET as the input, which determines whether multiple tasks are guaranteed to meet their deadlines. Formal models used for representing recurrent real-time tasks have traditionally been characterized by a collection of independent jobs that are released periodically. However, such a modeling may result in resource under-utilization in systems whose behaviors are not entirely periodic or independent. Examples are (i) multicore platforms where tasks share a communication fabric, like bus, for accesses to a shared memory beside processors; (ii) tasks with synchronization, where no two concurrent access to one shared resource are allowed to be in their critical section at the same time; and (iii) automotive systems, where tasks are linked to rotation (e.g., of the crankshaft, gears, or wheels). There, their activation rate is proportional to the angular velocity of a specific device. This dissertation presents multiple approaches towards designing scheduling algorithms and schedulability analysis for a variety of real-time systems with different characteristics. Specifically, we look at those design problems from the perspective of speedup factor — a metric that quantifies both the pessimism of the analysis and the non-optimality of the scheduling algorithm. The proposed solutions are shown promising by means of not only speedup factor but also extensive evaluations.},
adviser = {Prof. Dr. Jian-Jia Chen , Examiner: Prof. Dr. Jan Reineke (Uni Saarland)},
}
Real-time systems are designed for applications in which response time is critical. As timing is a major property of such systems, proving timing correctness is of utter importance. To achieve this, a two-fold approach of timing analysis is traditionally involved: (i) worst-case execution time (WCET) analysis, which computes an upper bound on the execution time of a single job of a task running in isolation; and (ii) schedulability analysis using the WCET as the input, which determines whether multiple tasks are guaranteed to meet their deadlines. Formal models used for representing recurrent real-time tasks have traditionally been characterized by a collection of independent jobs that are released periodically. However, such a modeling may result in resource under-utilization in systems whose behaviors are not entirely periodic or independent. Examples are (i) multicore platforms where tasks share a communication fabric, like bus, for accesses to a shared memory beside processors; (ii) tasks with synchronization, where no two concurrent access to one shared resource are allowed to be in their critical section at the same time; and (iii) automotive systems, where tasks are linked to rotation (e.g., of the crankshaft, gears, or wheels). There, their activation rate is proportional to the angular velocity of a specific device. This dissertation presents multiple approaches towards designing scheduling algorithms and schedulability analysis for a variety of real-time systems with different characteristics. Specifically, we look at those design problems from the perspective of speedup factor — a metric that quantifies both the pessimism of the analysis and the non-optimality of the scheduling algorithm. The proposed solutions are shown promising by means of not only speedup factor but also extensive evaluations.
- Mikail Yayla:
Deep Investigation for Fault Tolerance and Soft-Error Handling on Control Application.
March 2017, The enhancement of the thesis has been added in the downloadable version., B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, M.Sc. Kuan-Hsun Chen
[BibTeX]@bachelorthesis { yayla:2017,
title = {Deep Investigation for Fault Tolerance and Soft-Error Handling on Control Application},
author = {Yayla, Mikail},
year = {2017},
month = {March},
note = {The enhancement of the thesis has been added in the downloadable version.},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, M.Sc. Kuan-Hsun Chen},
}
- Pascal Libuschewski:
Exploration of Cyber-Physical Systems for GPGPU Computer Vision-Based Detection of Biological Viruses.
Dortmund, Germany, March 2017, PhD thesis, Adviser: Prof. Dr. Peter Marwedel
[BibTeX][PDF][Link][Abstract]@phdthesis { Libuschewski:2017:phdthesis,
title = {Exploration of Cyber-Physical Systems for GPGPU Computer Vision-Based Detection of Biological Viruses},
author = {Libuschewski, Pascal},
school = {TU Dortmund, Department of Computer Science},
year = {2017},
type = {Dissertation},
address = {Dortmund, Germany},
month = {March},
url = {http://dx.doi.org/10.17877/DE290R-17952},
keywords = {Biological viruses;Computer vision;Cyber-Physical Systems;Design space exploration;DSE;Embedded Systems;Energy-aware;GPGPU;GPU;medical image processing;Mobile sensor;Multi-objective;Optimization;Virus Detection},
file = {https://eldorado.tu-dortmund.de/bitstream/2003/35929/1/Dissertation_Libuschewski.pdf},
confidential = {n},
abstract = {This work presents a method for a computer vision-based detection of biological viruses in PAMONO sensor images and, related to this, methods to explore cyber-physical systems such as those consisting of the PAMONO sensor, the detection software, and processing hardware. The focus is especially on an exploration of Graphics Processing Units (GPU) hardware for ``General-Purpose computing on Graphics Processing Units'' (GPGPU) software and the targeted systems are high performance servers, desktop systems, mobile systems, and hand-held systems.},
adviser = {Prof. Dr. Peter Marwedel},
}
This work presents a method for a computer vision-based detection of biological viruses in PAMONO sensor images and, related to this, methods to explore cyber-physical systems such as those consisting of the PAMONO sensor, the detection software, and processing hardware. The focus is especially on an exploration of Graphics Processing Units (GPU) hardware for "General-Purpose computing on Graphics Processing Units" (GPGPU) software and the targeted systems are high performance servers, desktop systems, mobile systems, and hand-held systems.
2016
- Junjie Shi:
Implementation and Evaluation of Real-Time Multiprocessor Scheduling Algorithms on LITMUS-RT.
December 2016, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, M. Ing. Kevin Wen-Hung Huang
[BibTeX]@mastersthesis { junjie2016,
title = {Implementation and Evaluation of Real-Time Multiprocessor Scheduling Algorithms on LITMUS-RT},
author = {Shi, Junjie},
school = {TU Dortmund},
year = {2016},
month = {December},
keywords = {junjie},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, M. Ing. Kevin Wen-Hung Huang},
}
- Andreas Lang:
Ressourcengewahre Ablaufplanungsverfahren für modellbasierte Optimierungen.
September 2016, B.Sc. thesis, Adviser: Helena Kotthaus
[BibTeX]@bachelorthesis { lang:2016,
title = {Ressourcengewahre Ablaufplanungsverfahren f\"ur modellbasierte Optimierungen},
author = {Lang, Andreas},
year = {2016},
month = {September},
confidential = {n},
adviser = {Helena Kotthaus},
}
- Thomas Richter:
Automated Vehicle Telematic Data Acquisition and Information Transformation.
August 2016, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, Prof. Dr. Kristian Kersting
[BibTeX]@mastersthesis { Thomas2016,
title = {Automated Vehicle Telematic Data Acquisition and Information Transformation},
author = {Richter, Thomas},
school = {TU Dortmund},
year = {2016},
month = {August},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, Prof. Dr. Kristian Kersting},
}
- Dragana Popovic:
Saving Energy for Mobile Biosensors by Offloading.
May 2016, B.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, M. Ing. Kevin Wen-Hung Huang
[BibTeX]@bachelorthesis { Dragana2016,
title = {Saving Energy for Mobile Biosensors by Offloading},
author = {Popovic, Dragana},
school = {TU Dortmund},
year = {2016},
month = {May},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, M. Ing. Kevin Wen-Hung Huang},
}
- Sebastian Struwe:
Optimierung der Energieeffizienz von Real-Time Wireless Communications.
February 2016, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, Dipl. Inf. Ingo Korb
[BibTeX]@mastersthesis { Sebastian2016,
title = {Optimierung der Energieeffizienz von Real-Time Wireless Communications},
author = {Struwe, Sebastian},
school = {TU Dortmund},
year = {2016},
month = {February},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, Dipl. Inf. Ingo Korb},
}
2015
- Vasco Fachin:
Approximated Timing Analysis in Real-Time Calculus.
November 2015, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, M. Ing. Kevin Wen-Hung Huang
[BibTeX]@mastersthesis { Vasco2015,
title = {Approximated Timing Analysis in Real-Time Calculus},
author = {Fachin, Vasco},
school = {TU Dortmund},
year = {2015},
month = {November},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, M. Ing. Kevin Wen-Hung Huang},
}
- Huan Tian:
Design and Implementation of Computation Offloading Mechanism in Real-Time System.
July 2015, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen
[BibTeX]@mastersthesis { Huan2015,
title = {Design and Implementation of Computation Offloading Mechanism in Real-Time System},
author = {Tian, Huan},
school = {TU Dortmund},
year = {2015},
month = {July},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen},
}
- Venkata Rama Prasad Donda:
Stereo camera de-calibration detection based on observing kinematic attributes of detected objects and the camera rig.
July 2015, M.Sc. thesis, Adviser: Prof. Dr. Jian-Jia Chen, Marcel de Jong
[BibTeX]@mastersthesis { Venkata2015,
title = {Stereo camera de-calibration detection based on observing kinematic attributes of detected objects and the camera rig},
author = {Donda, Venkata Rama Prasad},
school = {TU Dortmund},
year = {2015},
month = {July},
confidential = {n},
adviser = {Prof. Dr. Jian-Jia Chen, Marcel de Jong},
}
- Martin Scholten:
Softwareredundanz zur Erkennung transienter Fehler.
March 2015, B.Sc. thesis, Adviser: Florian Schmoll
[BibTeX][PDF]@bachelorthesis { Scholten2015,
title = {Softwareredundanz zur Erkennung transienter Fehler},
author = {Scholten, Martin},
school = {Technische Universtit\"at Dortmund},
year = {2015},
month = {March},
keywords = {error detection, instruction duplication},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/scholten.pdf},
confidential = {n},
adviser = {Florian Schmoll},
}
- Timon Kelter:
WCET Analysis and Optimization for Multi-Core Real-Time Systems.
March 2015, PhD thesis, Adviser: Prof. Dr. Peter Marwedel
[BibTeX][PDF]@phdthesis { kelter:2015:phdthesis,
title = {WCET Analysis and Optimization for Multi-Core Real-Time Systems},
author = {Kelter, Timon},
school = {TU Dortmund, Department of Computer Science},
year = {2015},
month = {March},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/kelter-phd.pdf},
confidential = {n},
adviser = {Prof. Dr. Peter Marwedel},
}
2013
- Tim Harde:
Vergleichende Studie von Arbitrierungsverfahren für Kommunikationsstrukturen in eingebetteten Multicoresystemen.
2013, B.Sc. thesis, Adviser: Timon Kelter
[BibTeX][PDF]@bachelorthesis { harde:2013,
title = {Vergleichende Studie von Arbitrierungsverfahren f\"ur Kommunikationsstrukturen in eingebetteten Multicoresystemen},
author = {Harde, Tim},
school = {TU Dortmund},
year = {2013},
keywords = {wcet simulation},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/harde.pdf},
confidential = {n},
adviser = {Timon Kelter},
}
- Daniel A. Cordes:
Automatic Parallelization for Embedded Multi-Core Systems using High-Level Cost Models.
2013, PhD thesis
[BibTeX][Link]@phdthesis { Cordes:2013,
title = {Automatic Parallelization for Embedded Multi-Core Systems using High-Level Cost Models},
author = {Cordes, Daniel A.},
school = {TU Dortmund University},
year = {2013},
url = {http://hdl.handle.net/2003/31796},
confidential = {n},
}
- Christian Günter:
Unterstützung modularer WCET-Analyse durch annotierte Binärobjekte.
2013, B.Sc. thesis, Adviser: Timon Kelter
[BibTeX][PDF]@bachelorthesis { guenter:2013,
title = {Unterst\"utzung modularer WCET-Analyse durch annotierte Bin\"arobjekte},
author = {G\"unter, Christian},
school = {TU Dortmund},
year = {2013},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/guenter.pdf},
confidential = {n},
adviser = {Timon Kelter},
}
- Hendrik Borghorst:
Schedulingverfahren zur WCET-Reduktion in eingebetteten Multicore-Systemen.
2013, M.Sc. thesis, Adviser: Timon Kelter
[BibTeX][PDF]@mastersthesis { borghorst:2013,
title = {Schedulingverfahren zur WCET-Reduktion in eingebetteten Multicore-Systemen},
author = {Borghorst, Hendrik},
school = {TU Dortmund},
year = {2013},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/borghorst-ma.pdf},
confidential = {n},
adviser = {Timon Kelter},
}
2012
- Constantin Timm:
Resource Efficient Processing and Communication in Sensor/Actuator Environments.
2012, PhD thesis
[BibTeX][PDF][Link][Abstract]@phdthesis { ,
title = {Resource Efficient Processing and Communication in Sensor/Actuator Environments},
author = {Timm, Constantin},
school = {TU Dortmund, Department of Computer Science},
year = {2012},
type = {Dissertation},
url = {http://hdl.handle.net/2003/29731},
file = {https://eldorado.tu-dortmund.de/bitstream/2003/29731/1/Dissertation.pdf},
confidential = {n},
abstract = {The future of computer systems will not be dominated by personal computer like hardware platforms but by embedded and cyber-physical systems assisting humans in a hidden but omnipresent manner. These pervasive computing devices can, for example, be utilized in the home automation sector to create sensor/ actuator networks supporting the inhabitants of a house in everyday life. The efficient usage of resources is an important topic at design time and operation time of mobile embedded and cyber-physical systems. Therefore, this thesis presents methods which allow an efficient use of energy and processing resources in sensor/actuator networks. These networks comprise different nodes cooperating for a “smart” joint control function. Sensor/actuator nodes are typical cyber-physical systems comprising sensors/actuators and processing and communication components. Processing components of today’s sensor nodes can comprise many-core chips. This thesis introduces new methods for optimizing the code and the application mapping of the aforementioned systems and presents novel results with regard to design space explorations for energy-efficient and embedded many-core systems. The considered many-core systems are graphics processing units. The application code for these graphics processing units is optimized for a particular platform variant with the objectives of minimal energy consumption and/or of minimal runtime. These two objectives are targeted with the utilization of multi-objective optimization techniques. The mapping optimizations are realized by means of multi-objective design space explorations. Furthermore, this thesis introduces new techniques and functions for a resource-efficient middleware design employing service-oriented architectures. Therefore, a service-oriented architecture based middleware framework is presented which comprises a lightweight service orchestration. In addition to that, a flexible resource management mechanism will be introduced. This resource management adapts resource utilization and services to an environmental context and provides methods to reduce the energy consumption of sensor nodes.},
}
The future of computer systems will not be dominated by personal computer like hardware platforms but by embedded and cyber-physical systems assisting humans in a hidden but omnipresent manner. These pervasive computing devices can, for example, be utilized in the home automation sector to create sensor/ actuator networks supporting the inhabitants of a house in everyday life. The efficient usage of resources is an important topic at design time and operation time of mobile embedded and cyber-physical systems. Therefore, this thesis presents methods which allow an efficient use of energy and processing resources in sensor/actuator networks. These networks comprise different nodes cooperating for a “smart” joint control function. Sensor/actuator nodes are typical cyber-physical systems comprising sensors/actuators and processing and communication components. Processing components of today’s sensor nodes can comprise many-core chips. This thesis introduces new methods for optimizing the code and the application mapping of the aforementioned systems and presents novel results with regard to design space explorations for energy-efficient and embedded many-core systems. The considered many-core systems are graphics processing units. The application code for these graphics processing units is optimized for a particular platform variant with the objectives of minimal energy consumption and/or of minimal runtime. These two objectives are targeted with the utilization of multi-objective optimization techniques. The mapping optimizations are realized by means of multi-objective design space explorations. Furthermore, this thesis introduces new techniques and functions for a resource-efficient middleware design employing service-oriented architectures. Therefore, a service-oriented architecture based middleware framework is presented which comprises a lightweight service orchestration. In addition to that, a flexible resource management mechanism will be introduced. This resource management adapts resource utilization and services to an environmental context and provides methods to reduce the energy consumption of sensor nodes.
- Ingo Korb:
A Cross-Layer Analysis of Error Impact on the Instruction Execution in an 8-bit Microprocessor.
2012, Diplomarbeit, M.Sc. thesis, Adviser: Michael Engel
[BibTeX][PDF]@mastersthesis { Kor12,
title = {A Cross-Layer Analysis of Error Impact on the Instruction Execution in an 8-bit Microprocessor},
author = {Korb, Ingo},
school = {TU Dortmund},
year = {2012},
note = {Diplomarbeit},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2012-korb.pdf},
confidential = {n},
adviser = {Michael Engel},
}
- Dennis Nahberger:
Fehlerbehandlung in echtzeitfähigen Steueranwendungen.
2012, Diplomarbeit, M.Sc. thesis, Adviser: Andreas Heinig
[BibTeX]@mastersthesis { Nah12,
title = {Fehlerbehandlung in echtzeitf\"ahigen Steueranwendungen},
author = {Nahberger, Dennis},
school = {TU Dortmund},
year = {2012},
note = {Diplomarbeit},
confidential = {n},
adviser = {Andreas Heinig},
}
- Daniel Wippler:
Hochparallele echtzeitkonforme Datenextraktion aus QR-Markern.
2012, Diplomarbeit, M.Sc. thesis, Adviser: Constantin Timm
[BibTeX]@mastersthesis { wippler:2012,
title = {Hochparallele echtzeitkonforme Datenextraktion aus QR-Markern},
author = {Wippler, Daniel},
school = {TU Dortmund},
year = {2012},
note = {Diplomarbeit},
confidential = {n},
adviser = {Constantin Timm},
}
- Sascha Plazar:
Memory-based Optimization Techniques for Real-Time Systems.
Dortmund, Germany, July 2012, PhD thesis
[BibTeX][PDF][Link][Abstract]@phdthesis { plazar:12:diss,
title = {Memory-based Optimization Techniques for Real-Time Systems},
author = {Plazar, Sascha},
school = {TU Dortmund, Department of Computer Science},
year = {2012},
type = {Dissertation},
address = {Dortmund, Germany},
month = {jul},
url = {https://eldorado.tu-dortmund.de/handle/2003/29500},
keywords = {wcet},
file = {https://eldorado.tu-dortmund.de/bitstream/2003/29500/1/Dissertation.pdf},
confidential = {n},
abstract = {Embedded/Cyber-physical systems have become popular in a wide range of application scenarios. Such systems are called real-time systems if they underlie strict timing constraints. To verify if such systems can meet their deadlines, the knowledge of an upper bound for a program's execution time is mandatory. This upper bound is also called worst-case execution time (WCET) and is estimated by static timing analyzers. Established optimizing compilers are not aware of the WCET as objective since they focus on the minimization of the average-case execution time (ACET). To overcome this obstacle, this thesis presents memory-based optimization techniques which focus on the reduction of the WCET of programs. All presented optimizations are integrated into the WCET-aware C Compiler (WCC) framework. Since the memory interface of a system often turns out to be a bottleneck which limits the performance of a system, the presented optimizations are applied to different levels of the memory hierarchy of a system. Starting within a CPU core, the instruction fetch buffer is the most tightly coupled memory which tries to provide the next few instructions to be executed. Optimization techniques are presented improving the efficiency of this buffer w.r.t. the WCET of a system. Instruction caches placed between the CPU core and the main memory try to speed up accesses to the main memory by storing local copies in fast small cache memories. In order to improve the efficiency of this part of the memory hierarchy, a memory content selection approach is introduced which improves the WCET of a program by improving the cache performance. Due to the fact that multi-task systems are employed in almost all domains, this thesis presents elaborate extensions to a compiler supporting the compilation and WCET-aware optimization of multi-task systems. These extensions are exploited to develop a number of novel optimizations for systems running multiple tasks. As first optimization, a WCET-driven software-based cache partitioning demonstrates the effectiveness of considering the WCET for the optimization of a set of tasks. Furthermore, many embedded systems integrate so-called scratchpad memories (SPM) as tightly coupled memories. An optimization approach for SPM allocation in a multi-task scenario is proposed. Besides, a holistic view of memory architecture compilation considers a number of memory-based WCET optimizations and presents approaches for a combined application. Existing compiler frameworks which are able to consider the WCET during optimization are limited to a particular hardware platform. In order to support multiple platforms, this thesis presents techniques to extend an existing WCET-aware compiler framework. Based on these extensions, a novel static cache locking optimization selects memory blocks which are statically locked into the instruction cache driven by WCET reductions. Applying these optimizations, the WCET of real-time applications can be reduced by about 35% to 48%. These results underline the need for specialized WCET-driven optimization techniques integrated into a sophisticated compiler framework. Otherwise, immense optimization potential would remain unused resulting in oversized and thus costly Embedded/Cyber-physical systems.
},
}
Embedded/Cyber-physical systems have become popular in a wide range of application scenarios. Such systems are called real-time systems if they underlie strict timing constraints. To verify if such systems can meet their deadlines, the knowledge of an upper bound for a program's execution time is mandatory. This upper bound is also called worst-case execution time (WCET) and is estimated by static timing analyzers. Established optimizing compilers are not aware of the WCET as objective since they focus on the minimization of the average-case execution time (ACET). To overcome this obstacle, this thesis presents memory-based optimization techniques which focus on the reduction of the WCET of programs. All presented optimizations are integrated into the WCET-aware C Compiler (WCC) framework. Since the memory interface of a system often turns out to be a bottleneck which limits the performance of a system, the presented optimizations are applied to different levels of the memory hierarchy of a system. Starting within a CPU core, the instruction fetch buffer is the most tightly coupled memory which tries to provide the next few instructions to be executed. Optimization techniques are presented improving the efficiency of this buffer w.r.t. the WCET of a system. Instruction caches placed between the CPU core and the main memory try to speed up accesses to the main memory by storing local copies in fast small cache memories. In order to improve the efficiency of this part of the memory hierarchy, a memory content selection approach is introduced which improves the WCET of a program by improving the cache performance. Due to the fact that multi-task systems are employed in almost all domains, this thesis presents elaborate extensions to a compiler supporting the compilation and WCET-aware optimization of multi-task systems. These extensions are exploited to develop a number of novel optimizations for systems running multiple tasks. As first optimization, a WCET-driven software-based cache partitioning demonstrates the effectiveness of considering the WCET for the optimization of a set of tasks. Furthermore, many embedded systems integrate so-called scratchpad memories (SPM) as tightly coupled memories. An optimization approach for SPM allocation in a multi-task scenario is proposed. Besides, a holistic view of memory architecture compilation considers a number of memory-based WCET optimizations and presents approaches for a combined application. Existing compiler frameworks which are able to consider the WCET during optimization are limited to a particular hardware platform. In order to support multiple platforms, this thesis presents techniques to extend an existing WCET-aware compiler framework. Based on these extensions, a novel static cache locking optimization selects memory blocks which are statically locked into the instruction cache driven by WCET reductions. Applying these optimizations, the WCET of real-time applications can be reduced by about 35% to 48%. These results underline the need for specialized WCET-driven optimization techniques integrated into a sophisticated compiler framework. Otherwise, immense optimization potential would remain unused resulting in oversized and thus costly Embedded/Cyber-physical systems.
2011
- Christian Wessel:
GPU-basierte Generierung von Fräsbahnen im Kontext dentaler Anwendungsszenarien unter Beachtung multipler Ressourcenlimitierungen.
2011, M.Sc. thesis, Adviser: Constantin Timm
[BibTeX]@mastersthesis { wessel:2011,
title = {GPU-basierte Generierung von Fr\"asbahnen im Kontext dentaler Anwendungsszenarien unter Beachtung multipler Ressourcenlimitierungen},
author = {Wessel, Christian},
school = {TU Dortmund},
year = {2011},
confidential = {n},
adviser = {Constantin Timm},
}
- Patrick Vorlicek:
Ressourcenmodellierung und effiziente Ressourcennutzung im Kontext dezentraler Steuerungsprozesse in der Intralogistik.
2011, B.Sc. thesis, Adviser: Constantin Timm
[BibTeX]@bachelorthesis { Vorlicek:2011,
title = {Ressourcenmodellierung und effiziente Ressourcennutzung im Kontext dezentraler Steuerungsprozesse in der Intralogistik},
author = {Vorlicek, Patrick},
school = {TU Dortmund},
year = {2011},
confidential = {n},
adviser = {Constantin Timm},
}
- Markus Görlich:
Untersuchung und Verbesserung der Speicherzugriffsverteilung in GPGPU-Programmen unter Nutzung adaptiver Schedulingmethoden.
2011, M.Sc. thesis, Adviser: Constantin Timm
[BibTeX]@mastersthesis { goerlich:2011,
title = {Untersuchung und Verbesserung der Speicherzugriffsverteilung in GPGPU-Programmen unter Nutzung adaptiver Schedulingmethoden},
author = {G\"orlich, Markus},
school = {TU Dortmund},
year = {2011},
confidential = {n},
adviser = {Constantin Timm},
}
- Hendrik Borghorst:
WCET bewusste Scratchpad-Speicherallokation von Code und Daten für Multi-Task Systeme.
2011, B.Sc. thesis, Adviser: Sascha Plazar
[BibTeX][PDF]@bachelorthesis { Borghorst:2011,
title = {WCET bewusste Scratchpad-Speicherallokation von Code und Daten f\"ur Multi-Task Systeme},
author = {Borghorst, Hendrik},
school = {TU Dortmund},
year = {2011},
keywords = {wcet optimizations},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/borghorst.pdf},
confidential = {n},
adviser = {Sascha Plazar},
}
- Lars Rademacher:
Vergleich und Analyse von Checkpointing-Verfahren als Fehlerkorrekturmaßnahme in eingebetteten Systemen.
October 2011, B.Sc. thesis, Adviser: Florian Schmoll
[BibTeX]@bachelorthesis { Rademacher2011,
title = {Vergleich und Analyse von Checkpointing-Verfahren als Fehlerkorrekturma\"snahme in eingebetteten Systemen},
author = {Rademacher, Lars},
school = {Technische Universtit\"at Dortmund},
year = {2011},
month = {October},
keywords = {error correction},
confidential = {n},
adviser = {Florian Schmoll},
}
- Jens Möllmer:
WCET Optimierung unter Beachtung der Speicherhierarchie.
August 2011, B.Sc. thesis, Adviser: Sascha Plazar
[BibTeX][PDF]@bachelorthesis { Moellmer2011,
title = {WCET Optimierung unter Beachtung der Speicherhierarchie},
author = {M\"ollmer, Jens},
school = {Technische Universit\"at Dortmund},
year = {2011},
month = {August},
keywords = {wcet optimizations},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/moellmer.pdf},
confidential = {n},
adviser = {Sascha Plazar},
}
- Arthur Pyka:
Multikriterielle Exploration von Compileroptimierungen und Cacheparametern.
February 2011, M.Sc. thesis, Adviser: Sascha Plazar
[BibTeX][PDF]@mastersthesis { Pyka2011,
title = {Multikriterielle Exploration von Compileroptimierungen und Cacheparametern},
author = {Pyka, Arthur},
school = {Technische Universtit\"at Dortmund},
year = {2011},
month = {February},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/pyka.pdf},
confidential = {n},
adviser = {Sascha Plazar},
}
- Kyrill Risto:
Scratchpad-Allokation zur Reduktion der größtmöglichen Laufzeit von Multitask-Systemen.
January 2011, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX]@mastersthesis { Risto2011,
title = {Scratchpad-Allokation zur Reduktion der gr\"o\"stm\"oglichen Laufzeit von Multitask-Systemen},
author = {Risto, Kyrill},
school = {Technische Universtit\"at Dortmund},
year = {2011},
month = {January},
keywords = {wcet},
confidential = {n},
adviser = {Heiko Falk},
}
- Helena Kotthaus:
Cache-bewusste Code-Positionierung zur Reduktion der maximalen Programmlaufzeit (WCET).
January 2011, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX]@mastersthesis { Kotthaus2011,
title = {Cache-bewusste Code-Positionierung zur Reduktion der maximalen Programmlaufzeit (WCET)},
author = {Kotthaus, Helena},
school = {Technische Universtit\"at Dortmund},
year = {2011},
month = {January},
keywords = {wcet},
confidential = {n},
adviser = {Heiko Falk},
}
2010
- Andreas Koch:
Entwurf einer variablen Bildverarbeitungspipeline für Biosensoren auf FPGAs.
2010, B.Sc. thesis, Adviser: Peter Marwedel
[BibTeX]@bachelorthesis { Koch:2010,
title = {Entwurf einer variablen Bildverarbeitungspipeline f\"ur Biosensoren auf FPGAs},
author = {Koch, Andreas},
school = {TU Dortmund},
year = {2010},
confidential = {n},
adviser = {Peter Marwedel},
}
- Richard Hellwig:
Nutzbarkeitsanalyse von Schleifenparallelisierer für GPGPU-Anwendungen in Eingebetteten Systemen.
2010, B.Sc. thesis, Adviser: Constantin Timm
[BibTeX]@bachelorthesis { hellwig:2010,
title = {Nutzbarkeitsanalyse von Schleifenparallelisierer f\"ur GPGPU-Anwendungen in Eingebetteten Systemen},
author = {Hellwig, Richard},
school = {TU Dortmund},
year = {2010},
confidential = {n},
adviser = {Constantin Timm},
}
- Shen Lu:
High-Level Scratchpad-Memory Allokation für Programmcode mittels Clustering.
November 2010, M.Sc. thesis, Adviser: Florian Schmoll
[BibTeX]@mastersthesis { Lu2010,
title = {High-Level Scratchpad-Memory Allokation f\"ur Programmcode mittels Clustering},
author = {Lu, Shen},
school = {Technische Universtit\"at Dortmund},
year = {2010},
month = {November},
keywords = {spm},
confidential = {n},
adviser = {Florian Schmoll},
}
- Lutz Krumme:
Dynamische Scratchpad-Allokation von Code und Daten zur WCET-Minimierung.
August 2010, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Krumme2010,
title = {Dynamische Scratchpad-Allokation von Code und Daten zur WCET-Minimierung},
author = {Krumme, Lutz},
school = {Technische Universtit\"at Dortmund},
year = {2010},
month = {August},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/krumme.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Norman Schmitz:
ILP-basierte Registerallokation zur Worst-Case Execution Time Minimierung.
June 2010, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Schmitz2010,
title = {ILP-basierte Registerallokation zur Worst-Case Execution Time Minimierung},
author = {Schmitz, Norman},
school = {Technische Universtit\"at Dortmund},
year = {2010},
month = {June},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/schmitz.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Andre Smolarczyk:
Instruction Scheduling-Verfahren zur Minimierung der WCET.
May 2010, M.Sc. thesis, Adviser: Paul Lokuciejewski
[BibTeX][PDF]@mastersthesis { Smolarczyk2010,
title = {Instruction Scheduling-Verfahren zur Minimierung der WCET},
author = {Smolarczyk, Andre},
school = {Technische Universtit\"at Dortmund},
year = {2010},
month = {May},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/smolarczyk.pdf},
confidential = {n},
adviser = {Paul Lokuciejewski},
}
- Igor Ionov:
Design und Realisierung von Konzepten für retargierbare, multikriterielle Optimierungen im WCET-fähigen Compiler.
March 2010, M.Sc. thesis, Adviser: Sascha Plazar
[BibTeX][PDF]@mastersthesis { Ionov2010,
title = {Design und Realisierung von Konzepten f\"ur retargierbare, multikriterielle Optimierungen im WCET-f\"ahigen Compiler},
author = {Ionov, Igor},
school = {Technische Universtit\"at Dortmund},
year = {2010},
month = {March},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/ionov.pdf},
confidential = {n},
adviser = {Sascha Plazar},
}
2009
- Timon Kelter:
Superblock-basierte High-Level WCET-Optimierungen.
September 2009, M.Sc. thesis, Adviser: Paul Lokuciejewski
[BibTeX][PDF]@mastersthesis { Kelter2009,
title = {Superblock-basierte High-Level WCET-Optimierungen},
author = {Kelter, Timon},
school = {Technische Universtit\"at Dortmund},
year = {2009},
month = {September},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/kelter.pdf},
confidential = {n},
adviser = {Paul Lokuciejewski},
}
- Thomas Pucyk:
Lokale und Globale Instruction Scheduling-Verfahren für den TriCore Prozessor.
June 2009, M.Sc. thesis, Adviser: Paul Lokuciejewski
[BibTeX][PDF]@mastersthesis { Pucyk2009,
title = {Lokale und Globale Instruction Scheduling-Verfahren f\"ur den TriCore Prozessor},
author = {Pucyk, Thomas},
school = {Technische Universtit\"at Dortmund},
year = {2009},
month = {June},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/pucyk.pdf},
confidential = {n},
adviser = {Paul Lokuciejewski},
}
2008
- Kui Zhang:
Efficient HD content Display Export from Mobile Devices to HD Displays.
2008, M.Sc. thesis, Adviser: Constantin Timm
[BibTeX]@mastersthesis { zhang:2008,
title = {Efficient HD content Display Export from Mobile Devices to HD Displays},
author = {Zhang, Kui},
school = {TU Dortmund},
year = {2008},
confidential = {n},
adviser = {Constantin Timm},
}
- Sebastian Hanloh:
Analyse des Einflusses der Zeitscheibenl¨ange beim RoundRobin-Scheduling in Cache- und Scratchpadbasierten Systemen.
December 2008, M.Sc. thesis, Adviser: Olivera Jovanovic
[BibTeX][PDF]@mastersthesis { Hanloh2008,
title = {Analyse des Einflusses der Zeitscheibenl¨ange beim RoundRobin-Scheduling in Cache- und Scratchpadbasierten Systemen},
author = {Hanloh, Sebastian},
school = {Technische Universtit\"at Dortmund},
year = {2008},
month = {December},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/hanloh.pdf},
confidential = {n},
adviser = {Olivera Jovanovic},
}
- Stefan Wonneberger:
Kopplung von Scheduling- und Speicherallokationsstrategien zur Energieverbrauchsminimierung.
November 2008, M.Sc. thesis, Adviser: Robert Pyka
[BibTeX][PDF]@mastersthesis { Wonneberger2008,
title = {Kopplung von Scheduling- und Speicherallokationsstrategien zur Energieverbrauchsminimierung},
author = {Wonneberger, Stefan},
school = {Technische Universtit\"at Dortmund},
year = {2008},
month = {November},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/wonneberger.pdf},
confidential = {n},
adviser = {Robert Pyka},
}
- Fatih Gedikli:
Transformation und Ausnutzung von WCET-Informationen für High-Level Optimierungen.
September 2008, M.Sc. thesis, Adviser: Paul Lokuciejewski
[BibTeX][PDF]@mastersthesis { Gedikli2008,
title = {Transformation und Ausnutzung von WCET-Informationen f\"ur High-Level Optimierungen},
author = {Gedikli, Fatih},
school = {Technische Universtit\"at Dortmund},
year = {2008},
month = {September},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/gedikli.pdf},
confidential = {n},
adviser = {Paul Lokuciejewski},
}
- Florian Schmoll:
ILP-basierte Registerallokation unter Ausnutzung von WCET-Daten.
September 2008, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Schmoll2008,
title = {ILP-basierte Registerallokation unter Ausnutzung von WCET-Daten},
author = {Schmoll, Florian},
school = {Technische Universtit\"at Dortmund},
year = {2008},
month = {September},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/schmoll.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Jan Christopher Kleinsorge:
WCET-centric code allocation for scratchpad memories.
September 2008, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Kleinsorge2008,
title = {WCET-centric code allocation for scratchpad memories},
author = {Kleinsorge, Jan Christopher},
school = {Technische Universtit\"at Dortmund},
year = {2008},
month = {September},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/kleinsorge.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Felix Rotthowe:
Scratchpad-Allokation von Daten zur Worst-Case Execution Time Minimierung.
August 2008, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Rotthowe2008,
title = {Scratchpad-Allokation von Daten zur Worst-Case Execution Time Minimierung},
author = {Rotthowe, Felix},
school = {Technische Universtit\"at Dortmund},
year = {2008},
month = {August},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/rotthowe.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Alexander Katriniok:
Speicherhierarchie Design-Space-Exploration für den MPARM System-on-Chip Simulator.
June 2008, M.Sc. thesis, Adviser: Robert Pyka
[BibTeX][PDF]@mastersthesis { Katriniok2008,
title = {Speicherhierarchie Design-Space-Exploration f\"ur den MPARM System-on-Chip Simulator},
author = {Katriniok, Alexander},
school = {Technische Universtit\"at Dortmund},
year = {2008},
month = {June},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/katriniok.pdf},
confidential = {n},
adviser = {Robert Pyka},
}
- Daniel Cordes:
Schleifenanalyse für einen WCET-optimierenden Compiler basierend auf Abstrakter Interpretation und Polylib.
April 2008, M.Sc. thesis, Adviser: Paul Lokuciejewski
[BibTeX][PDF]@mastersthesis { Cordes2008,
title = {Schleifenanalyse f\"ur einen WCET-optimierenden Compiler basierend auf Abstrakter Interpretation und Polylib},
author = {Cordes, Daniel},
school = {Technische Universtit\"at Dortmund},
year = {2008},
month = {April},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/cordes.pdf},
confidential = {n},
adviser = {Paul Lokuciejewski},
}
2007
- Da He:
Automatisierung des Integratiostests bei eingebetteten Systemen.
November 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { He2007,
title = {Automatisierung des Integratiostests bei eingebetteten Systemen},
author = {He, Da},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {November},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Mike Duhm:
Modellbasierte Auswertung des Tests verteilter KFZ-Infotainmentsysteme im mobilen Einsatz.
October 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Duhm2007,
title = {Modellbasierte Auswertung des Tests verteilter KFZ-Infotainmentsysteme im mobilen Einsatz},
author = {Duhm, Mike},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {October},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Harald Günther:
Simulationsbasierte Bewertung der \"Ubertragungssicherheit von KFZ-Bussystemen unter Berücksichtigung von Parameterstreuungen.
October 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Guenther2007,
title = {Simulationsbasierte Bewertung der \"Ubertragungssicherheit von KFZ-Bussystemen unter Ber\"ucksichtigung von Parameterstreuungen},
author = {G\"unther, Harald},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {October},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Michael Schaten:
Barrierefreiheit eines interaktiven Glossars.
September 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Schaten2007,
title = {Barrierefreiheit eines interaktiven Glossars},
author = {Schaten, Michael},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {September},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Judith Ackermann:
Analyse der Zuverlässigkeit von KFZ-Motorsteuerungen mit der Fehlerbaumtechnik.
August 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Ackermann2007,
title = {Analyse der Zuverl\"assigkeit von KFZ-Motorsteuerungen mit der Fehlerbaumtechnik},
author = {Ackermann, Judith},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {August},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Rene Zeglin:
Echtzeitfähigkeit eines Testsystems zur Konformitätsprüfung von Flexray Kommunikationscontrollern.
July 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Zeglin2007,
title = {Echtzeitf\"ahigkeit eines Testsystems zur Konformit\"atspr\"ufung von Flexray Kommunikationscontrollern},
author = {Zeglin, Rene},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {July},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Mirko Sykorra:
Lösung partieller Differentialgleichungen mit gemischter Genauigkeit auf field programmable gate arrays (FPGAs).
July 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Sykorra2007,
title = {L\"osung partieller Differentialgleichungen mit gemischter Genauigkeit auf field programmable gate arrays (FPGAs)},
author = {Sykorra, Mirko},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {July},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Nina Grau:
Energieeffiziente kooperative Scheduling- und Speicherallokationstechniken für Multiprozess-Systeme.
June 2007, M.Sc. thesis, Adviser: Robert Pyka
[BibTeX]@mastersthesis { Grau2007,
title = {Energieeffiziente kooperative Scheduling- und Speicherallokationstechniken f\"ur Multiprozess-Systeme},
author = {Grau, Nina},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {June},
confidential = {n},
adviser = {Robert Pyka},
}
- Thorsten Pannenbäcker:
Beispielhafte Erarbeitung eines BITE-Konzeptes für künftige Avioniksysteme.
June 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Pannenbaecker2007,
title = {Beispielhafte Erarbeitung eines BITE-Konzeptes f\"ur k\"unftige Avioniksysteme},
author = {Pannenb\"acker, Thorsten},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {June},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Thorsten Koch:
Energy-efficient and dynamic resource management for mobile devices.
May 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Koch2007,
title = {Energy-efficient and dynamic resource management for mobile devices},
author = {Koch, Thorsten},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {May},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Tobias Wegner:
Einsatz von Standard Hard- und Software im zeitkritischen Unternehmenrbetrieb am Beispiel von Windows XP in Kombination mit Profinet.
May 2007, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Wegner2007,
title = {Einsatz von Standard Hard- und Software im zeitkritischen Unternehmenrbetrieb am Beispiel von Windows XP in Kombination mit Profinet},
author = {Wegner, Tobias},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {May},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Daniel Höcker:
Effiziente Darstellung und Nutzung von WCET Pfad Analysen.
May 2007, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX]@mastersthesis { Hoecker2007,
title = {Effiziente Darstellung und Nutzung von WCET Pfad Analysen},
author = {H\"ocker, Daniel},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {May},
keywords = {wcet},
confidential = {n},
adviser = {Heiko Falk},
}
- Daniel Schulte:
Modellierung und Transformation von Flow Facts in einem WCET-optimierenden Compiler.
May 2007, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Schulte2007,
title = {Modellierung und Transformation von Flow Facts in einem WCET-optimierenden Compiler},
author = {Schulte, Daniel},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {May},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/schulte.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Sascha Plazar:
Einfluss von statischem Cache Locking auf Worst Case Execution Times.
January 2007, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Plazar2007,
title = {Einfluss von statischem Cache Locking auf Worst Case Execution Times},
author = {Plazar, Sascha},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {January},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/plazar.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Martin Schwarzer:
Untersuchung des Einflusses von Compiler-Optimierungen auf die Maximale Programm-Laufzeit (WCET).
January 2007, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Schwarzer2007,
title = {Untersuchung des Einflusses von Compiler-Optimierungen auf die Maximale Programm-Laufzeit (WCET)},
author = {Schwarzer, Martin},
school = {Technische Universtit\"at Dortmund},
year = {2007},
month = {January},
keywords = {wcet},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/schwarzer.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
2006
- Monika Enns:
Konzeption und Realisierung einer geschlossenen Toolchain zur entwicklungsbegleitenden Testautomatisierung von KFZ-Infotainmentsystemen.
2006, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Enns2006,
title = {Konzeption und Realisierung einer geschlossenen Toolchain zur entwicklungsbegleitenden Testautomatisierung von KFZ-Infotainmentsystemen},
author = {Enns, Monika},
school = {Technische Universtit\"at Dortmund},
year = {2006},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Olivera Jovanovic:
Dynamic Voltage Selection for energy efficient real-time multiprocessors.
November 2006, M.Sc. thesis, Adviser: Prof. Dr. Marwedel, Prof. Dr. Petru Eles
[BibTeX][PDF]@mastersthesis { Jovanovic2006,
title = {Dynamic Voltage Selection for energy efficient real-time multiprocessors},
author = {Jovanovic, Olivera},
school = {Technische Universtit\"at Dortmund},
year = {2006},
month = {November},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/jovanovic.pdf},
confidential = {n},
adviser = {Prof. Dr. Marwedel, Prof. Dr. Petru Eles},
}
- Christoph Faßbach:
Energieoptimierende, betriebssystemunterstützte, online Scratchpad-Allokation für Multiprozess-Applikationen.
September 2006, M.Sc. thesis, Adviser: Robert Pyka
[BibTeX][PDF]@mastersthesis { Fassbach2006,
title = {Energieoptimierende, betriebssystemunterst\"utzte, online Scratchpad-Allokation f\"ur Multiprozess-Applikationen},
author = {Fa\"sbach, Christoph},
school = {Technische Universtit\"at Dortmund},
year = {2006},
month = {September},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/fassbach.pdf.gz},
confidential = {n},
adviser = {Robert Pyka},
}
- Dirk Foersterling:
Interaktive Visualisierung der Medienzugriffskontrolle beim FlexRay-Protokoll.
September 2006, M.Sc. thesis, Adviser: Birgit Sirocic
[BibTeX][PDF]@mastersthesis { Foersterling2006,
title = {Interaktive Visualisierung der Medienzugriffskontrolle beim FlexRay-Protokoll},
author = {Foersterling, Dirk},
school = {Technische Universtit\"at Dortmund},
year = {2006},
month = {September},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/foersterling.pdf.gz},
confidential = {n},
adviser = {Birgit Sirocic},
}
- Andreas Volgmann:
Evaluation von Performance Parametern in einem ZigBee Netzwerke.
August 2006, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Volgmann2006,
title = {Evaluation von Performance Parametern in einem ZigBee Netzwerke},
author = {Volgmann, Andreas},
school = {Technische Universtit\"at Dortmund},
year = {2006},
month = {August},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Thomas Kindler:
Entwicklung von Hardware und Software für einen zweibeinigen Roboter.
April 2006, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Kindler2006,
title = {Entwicklung von Hardware und Software f\"ur einen zweibeinigen Roboter},
author = {Kindler, Thomas},
school = {Technische Universtit\"at Dortmund},
year = {2006},
month = {April},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Oliver Grätz:
Konzeption eines internetbasierten Audio-\"Ubertragungssystems auf der Basis Fragmentierter \"Ubertragung.
March 2006, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Graetz2006,
title = {Konzeption eines internetbasierten Audio-\"Ubertragungssystems auf der Basis Fragmentierter \"Ubertragung},
author = {Gr\"atz, Oliver},
school = {Technische Universtit\"at Dortmund},
year = {2006},
month = {March},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Alexandra Nolte-Spicker:
Interaktive Visualisierung von Weg-Zeit-Diagrammen.
March 2006, M.Sc. thesis, Adviser: Birgit Sirocic
[BibTeX]@mastersthesis { Nolte-Spicker2006,
title = {Interaktive Visualisierung von Weg-Zeit-Diagrammen},
author = {Nolte-Spicker, Alexandra},
school = {Technische Universtit\"at Dortmund},
year = {2006},
month = {March},
confidential = {n},
adviser = {Birgit Sirocic},
}
2005
- Paul Lokuciejewski:
Design and Realization of Concepts for WCET Compiler Optimization.
Decmber 2005, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX]@mastersthesis { Lokuciejewski2005,
title = {Design and Realization of Concepts for WCET Compiler Optimization},
author = {Lokuciejewski, Paul},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {Decmber},
keywords = {wcet},
confidential = {n},
adviser = {Heiko Falk},
}
- Lei Yao:
Vergleich von Bereichs- und Bitwertanalyse auf Registerebene.
November 2005, M.Sc. thesis, Adviser: Jens Wagner
[BibTeX]@mastersthesis { Yao2005,
title = {Vergleich von Bereichs- und Bitwertanalyse auf Registerebene},
author = {Yao, Lei},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {November},
confidential = {n},
adviser = {Jens Wagner},
}
- Holger Bihr:
Entwicklung einer plattformunabhängigen, kontext-sensitiven Aliasanalyse für das ICD-C Compiler-Framework.
November 2005, M.Sc. thesis, Adviser: Robert Pyka
[BibTeX]@mastersthesis { Bihr2005,
title = {Entwicklung einer plattformunabh\"angigen, kontext-sensitiven Aliasanalyse f\"ur das ICD-C Compiler-Framework},
author = {Bihr, Holger},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {November},
confidential = {n},
adviser = {Robert Pyka},
}
- Thorsten Wilmer:
Energieeffiziente Belegung von Scratchpad-Speichern mit Code und Arrays durch Loop-Tiling.
November 2005, M.Sc. thesis, Adviser: Lars Wehmeyer
[BibTeX][PDF]@mastersthesis { Wilmer2005,
title = {Energieeffiziente Belegung von Scratchpad-Speichern mit Code und Arrays durch Loop-Tiling},
author = {Wilmer, Thorsten},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {November},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/wilmer.pdf.gz},
confidential = {n},
adviser = {Lars Wehmeyer},
}
- Martin Piayda:
Entwicklung eines Gateways zwischen UPnP und EIB unter Verwendung von OSGI.
October 2005, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Piayda2005,
title = {Entwicklung eines Gateways zwischen UPnP und EIB unter Verwendung von OSGI},
author = {Piayda, Martin},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {October},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Daniel Barisic:
Konzipierung und Aufbau eines Entwicklungsframework für Softwarekomponenten Smarter UPnP Transceiver.
October 2005, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Barisic2005,
title = {Konzipierung und Aufbau eines Entwicklungsframework f\"ur Softwarekomponenten Smarter UPnP Transceiver},
author = {Barisic, Daniel},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {October},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Sebastian Schmidt Pedram Hadjian:
Voxelerator - a FPGA-based Volume Visualization Pipeline.
October 2005, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { PedramHadjian2005,
title = {Voxelerator - a FPGA-based Volume Visualization Pipeline},
author = {Pedram Hadjian, Sebastian Schmidt},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {October},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Désirée Kraus:
Definition und Integration einer Teilmenge von C++ als Zwischendarstellung in einer Compiler-Umgebung für eingebettete Systeme.
September 2005, M.Sc. thesis, Adviser: Jens Wagner
[BibTeX]@mastersthesis { Kraus2005,
title = {Definition und Integration einer Teilmenge von C++ als Zwischendarstellung in einer Compiler-Umgebung f\"ur eingebettete Systeme},
author = {Kraus, D\'esir\'ee},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {September},
confidential = {n},
adviser = {Jens Wagner},
}
- Daniel Fengler:
Evaluierung des Publish/Subscribe Messaging Paradigmas zur Kommunikation in OSGi Frameworks im Automobilumfeld.
September 2005, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Fengler2005,
title = {Evaluierung des Publish/Subscribe Messaging Paradigmas zur Kommunikation in OSGi Frameworks im Automobilumfeld},
author = {Fengler, Daniel},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {September},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Michael Engel:
Advancing Operating Systems via Aspect-Oriented Programming.
July 2005, PhD thesis
[BibTeX][PDF]@phdthesis { engel:05:diss,
title = {Advancing Operating Systems via Aspect-Oriented Programming},
author = {Engel, Michael},
school = {Philipps-Universit{\"a}t Marburg, Fachbereich Mathematik und Informatik},
year = {2005},
type = {Dissertation},
month = {July},
file = {http://archiv.ub.uni-marburg.de/diss/z2006/0138/pdf/dme.pdf},
confidential = {n},
}
- Vedran Divkovic:
Visuell rückgekoppelte ergometrische Belastungsprozesse: Entwurf, Realisierung und Test von geeigneten Geräten.
June 2005, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Divkovic2005,
title = {Visuell r\"uckgekoppelte ergometrische Belastungsprozesse: Entwurf, Realisierung und Test von geeigneten Ger\"aten},
author = {Divkovic, Vedran},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {June},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- David Hec:
Evaluierung von Postpassoptimierungen.
May 2005, M.Sc. thesis, Adviser: Jens Wagner
[BibTeX]@mastersthesis { Hec2005,
title = {Evaluierung von Postpassoptimierungen},
author = {Hec, David},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {May},
confidential = {n},
adviser = {Jens Wagner},
}
- Duy Khuong Nguyen:
Evaluierung von Fehlererkennungs-, Fehlerbehandlungs- und Redundanzmechanismen für concubiNet.
April 2005, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Nguyen2005,
title = {Evaluierung von Fehlererkennungs-, Fehlerbehandlungs- und Redundanzmechanismen f\"ur concubiNet},
author = {Nguyen, Duy Khuong},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {April},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- André Schaefer:
Performance-Optimierung in Eingebetteten Systemen durch automatische Ausnutzung von Prozessor-Merkmalen auf Quellcode-Ebene.
March 2005, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Schaefer2005,
title = {Performance-Optimierung in Eingebetteten Systemen durch automatische Ausnutzung von Prozessor-Merkmalen auf Quellcode-Ebene},
author = {Schaefer, Andr\'e},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {March},
keywords = {sco},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/schaefer.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Jinglu Han:
Interaktive Visualisierung von Real-Time Scheduling-Algorithmen.
January 2005, M.Sc. thesis, Adviser: Birgit Sirocic
[BibTeX]@mastersthesis { Han2005,
title = {Interaktive Visualisierung von Real-Time Scheduling-Algorithmen},
author = {Han, Jinglu},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {January},
confidential = {n},
adviser = {Birgit Sirocic},
}
- André Kernchen:
Compilergestütze Energiereduktion für SDRAM- und Flash-basierte Speichertechnologien.
January 2005, M.Sc. thesis, Adviser: Lars Wehmeyer
[BibTeX][PDF]@mastersthesis { Kernchen2005,
title = {Compilergest\"utze Energiereduktion f\"ur SDRAM- und Flash-basierte Speichertechnologien},
author = {Kernchen, Andr\'e},
school = {Technische Universtit\"at Dortmund},
year = {2005},
month = {January},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/kernchen.pdf.gz},
confidential = {n},
adviser = {Lars Wehmeyer},
}
2004
- Mark Rzepka:
Methodik der Konfiguration von wiederverwendbarer Lenksäulenapplikations-Software.
December 2004, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX]@mastersthesis { Rzepka2004,
title = {Methodik der Konfiguration von wiederverwendbarer Lenks\"aulenapplikations-Software},
author = {Rzepka, Mark},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {December},
confidential = {n},
adviser = {Stefan Steinke},
}
- Till Buchwald:
Plattformabhängigkeit der Effizienz von Schleifentransformationen auf der Quellcodeebene.
December 2004, M.Sc. thesis, Adviser: Sergej Schwenk
[BibTeX]@mastersthesis { Buchwald2004,
title = {Plattformabh\"angigkeit der Effizienz von Schleifentransformationen auf der Quellcodeebene},
author = {Buchwald, Till},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {December},
confidential = {n},
adviser = {Sergej Schwenk},
}
- Tobias Stricker:
Optimierung und Simulation dichter WLAN-Netzwerke mit QoS-Anforderungen.
December 2004, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Stricker2004,
title = {Optimierung und Simulation dichter WLAN-Netzwerke mit QoS-Anforderungen},
author = {Stricker, Tobias},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {December},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Mario Wallmeyer:
Entwicklung eines Navigationsverfahrens für Reinigungsroboter auf Basis von Transpondern.
December 2004, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Wallmeyer2004,
title = {Entwicklung eines Navigationsverfahrens f\"ur Reinigungsroboter auf Basis von Transpondern},
author = {Wallmeyer, Mario},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {December},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Markus Pilz:
Interaktive Visualisierung von Prozessnetzwerken.
November 2004, M.Sc. thesis, Adviser: Birgit Sirocic
[BibTeX]@mastersthesis { Pilz2004,
title = {Interaktive Visualisierung von Prozessnetzwerken},
author = {Pilz, Markus},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {November},
confidential = {n},
adviser = {Birgit Sirocic},
}
- Björn Elmar Schmidt:
Verteilte Datenhaltung in einem Location Based Service-System.
November 2004, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Schmidt2004,
title = {Verteilte Datenhaltung in einem Location Based Service-System},
author = {Schmidt, Bj\"orn Elmar},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {November},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Babak Davani:
EKG-Auswertung auf Mobilfunkgeräten.
October 2004, M.Sc. thesis, Adviser: Prof. Dr. Igel, Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Davani2004,
title = {EKG-Auswertung auf Mobilfunkger\"aten},
author = {Davani, Babak},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {October},
confidential = {n},
adviser = {Prof. Dr. Igel, Prof. Dr. Marwedel},
}
- Klaus Petzold:
Scratchpad-Allokations-Strategien für Multiprozess-Systeme.
October 2004, M.Sc. thesis, Adviser: Manish Verma, Lars Wehmeyer
[BibTeX][PDF]@mastersthesis { Petzold2004,
title = {Scratchpad-Allokations-Strategien f\"ur Multiprozess-Systeme},
author = {Petzold, Klaus},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {October},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/petzold.pdf.gz},
confidential = {n},
adviser = {Manish Verma, Lars Wehmeyer},
}
- Gregor Standers:
Entwurf eines Entwicklungsprozesses für sicherheitskritische Steuergeräte im Automobil.
October 2004, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX]@mastersthesis { Standers2004,
title = {Entwurf eines Entwicklungsprozesses f\"ur sicherheitskritische Steuerger\"ate im Automobil},
author = {Standers, Gregor},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {October},
confidential = {n},
adviser = {Stefan Steinke},
}
- Michael Vogt:
Plattformabhängige Eliminierung gemeinsamer Teilausdrücke auf Quellcode-Ebene.
September 2004, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Vogt2004,
title = {Plattformabh\"angige Eliminierung gemeinsamer Teilausdr\"ucke auf Quellcode-Ebene},
author = {Vogt, Michael},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {September},
keywords = {sco},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/vogt.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Heiko Falk:
Source Code Optimization Techniques for Data Flow Dominated Embedded Software.
June 2004, PhD thesis
[BibTeX][PDF]@phdthesis { Falk:04:phd,
title = {Source Code Optimization Techniques for Data Flow Dominated Embedded Software},
author = {Falk, Heiko},
school = {TU Dortmund, Faculty of Computer Science 12},
year = {2004},
month = {June},
keywords = {sco},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/phd-falk.pdf},
confidential = {n},
}
- Rafael König:
Entwicklung und Implementierung eines Routing-Protokolls für Bluetooth Ad-Hoc Netzwerke.
May 2004, M.Sc. thesis, Adviser: Prof. Dr. Marwedel
[BibTeX]@mastersthesis { Koenig2004,
title = {Entwicklung und Implementierung eines Routing-Protokolls f\"ur Bluetooth Ad-Hoc Netzwerke},
author = {K\"onig, Rafael},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {May},
confidential = {n},
adviser = {Prof. Dr. Marwedel},
}
- Katharina Kutyniok:
Optimierung zur Ausnutzung von SIMD Operationen und Festkommadatentypen unter Benutzung bitgenauer Datenflussanalyse.
April 2004, M.Sc. thesis, Adviser: Jens Wagner
[BibTeX]@mastersthesis { Kutyniok2004,
title = {Optimierung zur Ausnutzung von SIMD Operationen und Festkommadatentypen unter Benutzung bitgenauer Datenflussanalyse},
author = {Kutyniok, Katharina},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {April},
confidential = {n},
adviser = {Jens Wagner},
}
- Daniel Smolinski:
Benefits from revirtualization of Infineon TriCore registers.
April 2004, M.Sc. thesis, Adviser: Jens Wagner
[BibTeX]@mastersthesis { Smolinski2004,
title = {Benefits from revirtualization of Infineon TriCore registers},
author = {Smolinski, Daniel},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {April},
confidential = {n},
adviser = {Jens Wagner},
}
- Urs Helmig:
Compilergestützte Optimierung von Zugriffen auf partitionierte Speicher.
March 2004, M.Sc. thesis, Adviser: Lars Wehmeyer
[BibTeX][PDF]@mastersthesis { Helmig2004,
title = {Compilergest\"utzte Optimierung von Zugriffen auf partitionierte Speicher},
author = {Helmig, Urs},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {March},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/helmig.pdf.gz},
confidential = {n},
adviser = {Lars Wehmeyer},
}
- Jörg Kamphausen:
Entwicklung eines generischen Codegenerators für RISC-Architekturen.
January 2004, M.Sc. thesis, Adviser: Markus Lorenz
[BibTeX][PDF]@mastersthesis { Kamphausen2004,
title = {Entwicklung eines generischen Codegenerators f\"ur RISC-Architekturen},
author = {Kamphausen, J\"org},
school = {Technische Universtit\"at Dortmund},
year = {2004},
month = {January},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/kamphausen.pdf.gz},
confidential = {n},
adviser = {Markus Lorenz},
}
2003
- Robert Pyka:
Retargierbare Bitlevel Optimierungen für den Infineon Tricore Prozessor.
August 2003, M.Sc. thesis, Adviser: Jens Wagner
[BibTeX]@mastersthesis { Pyka2003,
title = {Retargierbare Bitlevel Optimierungen f\"ur den Infineon Tricore Prozessor},
author = {Pyka, Robert},
school = {Technische Universtit\"at Dortmund},
year = {2003},
month = {August},
confidential = {n},
adviser = {Jens Wagner},
}
- Peter Imhoff:
Codegrößenreduktion eingebetteter Systeme durch kombiniertes In- und Exlining.
August 2003, M.Sc. thesis, Adviser: Jens Wagner
[BibTeX][PDF]@mastersthesis { Imhoff2003,
title = {Codegr\"o\"senreduktion eingebetteter Systeme durch kombiniertes In- und Exlining},
author = {Imhoff, Peter},
school = {Technische Universtit\"at Dortmund},
year = {2003},
month = {August},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/imhoff.pdf.gz},
confidential = {n},
adviser = {Jens Wagner},
}
2002
- Michael Engel:
Entwurf und Implementierung eines ad-hoc Netzwerks für Mobilgeräte.
2002, M.Sc. thesis
[BibTeX]@mastersthesis { engel:02:informatik,
title = {Entwurf und Implementierung eines ad-hoc Netzwerks f{\"u}r Mobilger{\"a}te},
author = {Engel, Michael},
school = {Universit{\"a}t Siegen, Fachbereich Elektrotechnik und Informatik},
year = {2002},
type = {Diplomarbeit},
confidential = {n},
}
- Nils Grunwald:
Energieminimierung eingebetteter Programme durch die dynamische Nutzung eines Scratchpad-Speichers.
April 2002, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX][PDF]@mastersthesis { Grunwald2002,
title = {Energieminimierung eingebetteter Programme durch die dynamische Nutzung eines Scratchpad-Speichers},
author = {Grunwald, Nils},
school = {Technische Universtit\"at Dortmund},
year = {2002},
month = {April},
keywords = {ecc},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/grunwald.pdf.gz},
confidential = {n},
adviser = {Stefan Steinke},
}
- Jacek Jakubowski:
Architekturunabhängige Quellcodeoptimierung durch Mustererkennung.
April 2002, M.Sc. thesis, Adviser: Heiko Falk
[BibTeX][PDF]@mastersthesis { Jakubowski2002,
title = {Architekturunabh\"angige Quellcodeoptimierung durch Mustererkennung},
author = {Jakubowski, Jacek},
school = {Technische Universtit\"at Dortmund},
year = {2002},
month = {April},
keywords = {sco},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/jakubowski.pdf},
confidential = {n},
adviser = {Heiko Falk},
}
- Thomas Hüls:
Energieoptimierung einer MPEG-Applikation.
March 2002, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX][PDF]@mastersthesis { Huels2002,
title = {Energieoptimierung einer MPEG-Applikation},
author = {H\"uls, Thomas},
school = {Technische Universtit\"at Dortmund},
year = {2002},
month = {March},
keywords = {ecc},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/huels.pdf.gz},
confidential = {n},
adviser = {Stefan Steinke},
}
- Sergej Schwenk:
Entwicklung eines Energiemodells fuer den LEON Prozessor.
March 2002, M.Sc. thesis, Adviser: Lars Wehmeyer
[BibTeX]@mastersthesis { Schwenk2002,
title = {Entwicklung eines Energiemodells fuer den LEON Prozessor},
author = {Schwenk, Sergej},
school = {Technische Universtit\"at Dortmund},
year = {2002},
month = {March},
confidential = {n},
adviser = {Lars Wehmeyer},
}
2001
- Martin Horst:
Schleifenoptimierungen zur Ausnutzung paralleler Rechenwerke von Prozessoren der M3-DSP Plattform.
Novermber 2001, M.Sc. thesis, Adviser: Markus Lorenz
[BibTeX][PDF]@mastersthesis { Horst2001,
title = {Schleifenoptimierungen zur Ausnutzung paralleler Rechenwerke von Prozessoren der M3-DSP Plattform},
author = {Horst, Martin},
school = {Technische Universtit\"at Dortmund},
year = {2001},
month = {Novermber},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/horst.pdf.gz},
confidential = {n},
adviser = {Markus Lorenz},
}
- Markus Fiesel:
http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/fiesel.ps.gz.
December 2001, M.Sc. thesis, Adviser: Markus Lorenz
[BibTeX][PDF]@mastersthesis { Fiesel2001,
title = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/fiesel.ps.gz},
author = {Fiesel, Markus},
school = {Technische Universtit\"at Dortmund},
year = {2001},
month = {December},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/fiesel.ps.gz},
confidential = {n},
adviser = {Markus Lorenz},
}
- Lars Hornbach:
Generische Low-Level Optimierungen für RISC-Architekturen.
November 2001, M.Sc. thesis, Adviser: Lars Wehmeyer
[BibTeX][PDF]@mastersthesis { Hornbach2001,
title = {Generische Low-Level Optimierungen f\"ur RISC-Architekturen},
author = {Hornbach, Lars},
school = {Technische Universtit\"at Dortmund},
year = {2001},
month = {November},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/hornbach.ps.gz},
confidential = {n},
adviser = {Lars Wehmeyer},
}
- Bo-Sik Lee:
Vergleich des Energieverbrauchs von Cache- und Scratch-Pad-Speichern für den ARM7-Prozessor.
October 2001, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX][PDF]@mastersthesis { Lee2001,
title = {Vergleich des Energieverbrauchs von Cache- und Scratch-Pad-Speichern f\"ur den ARM7-Prozessor},
author = {Lee, Bo-Sik},
school = {Technische Universtit\"at Dortmund},
year = {2001},
month = {October},
keywords = {ecc},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/lee.ps.gz},
confidential = {n},
adviser = {Stefan Steinke},
}
- Christoph Zobiegala:
Energieeinsparung durch compilergesteuerte Nutzung des On-Chip-Speichers.
September 2001, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX][PDF]@mastersthesis { Zobiegala2001,
title = {Energieeinsparung durch compilergesteuerte Nutzung des On-Chip-Speichers},
author = {Zobiegala, Christoph},
school = {Technische Universtit\"at Dortmund},
year = {2001},
month = {September},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/zobiegala.ps.gz},
confidential = {n},
adviser = {Stefan Steinke},
}
- Markus Knauer:
Codierungsverfahren zur Reduktion des Energiebedarfs von Programmen.
July 2001, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX][PDF]@mastersthesis { Knauer2001,
title = {Codierungsverfahren zur Reduktion des Energiebedarfs von Programmen},
author = {Knauer, Markus},
school = {Technische Universtit\"at Dortmund},
year = {2001},
month = {July},
keywords = {ecc},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/knauer.ps.gz},
confidential = {n},
adviser = {Stefan Steinke},
}
- Gregory Sapsford:
Messung des Energieverbrauchs von Caches am Beispiel des StrongARM-Prozessors (Studienarbeit).
March 2001, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX][PDF]@mastersthesis { Sapsford2001,
title = {Messung des Energieverbrauchs von Caches am Beispiel des StrongARM-Prozessors (Studienarbeit)},
author = {Sapsford, Gregory},
school = {Technische Universtit\"at Dortmund},
year = {2001},
month = {March},
keywords = {ecc},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/sapsford.ps.gz},
confidential = {n},
adviser = {Stefan Steinke},
}
2000
- Michael Theokharidis:
Energiemessung von ARM7TDMI Prozessor-Instruktionen.
November 2000, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX][PDF]@mastersthesis { Theokharidis2000,
title = {Energiemessung von ARM7TDMI Prozessor-Instruktionen},
author = {Theokharidis, Michael},
school = {Technische Universtit\"at Dortmund},
year = {2000},
month = {November},
keywords = {ecc},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/theokharidis.ps.gz},
confidential = {n},
adviser = {Stefan Steinke},
}
- Ruediger Schwarz:
Reduktion des Energiebedarfs von Programmen für den ARM-Prozessor durch Registerpipelining.
September 2000, M.Sc. thesis, Adviser: Stefan Steinke
[BibTeX][PDF]@mastersthesis { schwarz:00:thesis,
title = {Reduktion des Energiebedarfs von Programmen f\"ur den ARM-Prozessor durch Registerpipelining},
author = {Schwarz, Ruediger},
school = {TU Dortmund, Faculty of Computer Science 12},
year = {2000},
month = {sep},
file = {media/documents/theses/schwarz.pdf.gz},
confidential = {n},
adviser = {Stefan Steinke},
}
- David Kottmann:
Adresszuweisung fuer den M3-DSP.
June 2000, M.Sc. thesis, Adviser: Markus Lorenz
[BibTeX][PDF]@mastersthesis { Kottmann2000,
title = {Adresszuweisung fuer den M3-DSP},
author = {Kottmann, David},
school = {Technische Universtit\"at Dortmund},
year = {2000},
month = {June},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/kottmann.ps.gz},
confidential = {n},
adviser = {Markus Lorenz},
}
- Frank Jagla:
Uebersetzung und Optimierung objektorientierter Programmiersprachen unter besonderer Beruecksichtigung eingebetteter Systeme.
May 2000, M.Sc. thesis, Adviser: Steven Bashrod
[BibTeX][PDF]@mastersthesis { Jagla2000,
title = {Uebersetzung und Optimierung objektorientierter Programmiersprachen unter besonderer Beruecksichtigung eingebetteter Systeme},
author = {Jagla, Frank},
school = {Technische Universtit\"at Dortmund},
year = {2000},
month = {May},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/jagla.pdf},
confidential = {n},
adviser = {Steven Bashrod},
}
- Daniel Kotte:
Speicherpartitionierung in DSP-Compilern.
April 2000, M.Sc. thesis, Adviser: Rainer Leupers
[BibTeX][PDF]@mastersthesis { Kotte2000,
title = {Speicherpartitionierung in DSP-Compilern},
author = {Kotte, Daniel},
school = {Technische Universtit\"at Dortmund},
year = {2000},
month = {April},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/kotte.ps.gz},
confidential = {n},
adviser = {Rainer Leupers},
}
1999
- Michael Engel:
Lösung von Finite-Elemente-Problemen mit MODULEF.
1999, M.Sc. thesis
[BibTeX]@mastersthesis { engel:99:mathe,
title = {L{\"o}sung von Finite-Elemente-Problemen mit MODULEF},
author = {Engel, Michael},
school = {Universit{\"a}t Siegen, Fachbereich Mathematik},
year = {1999},
type = {Diplomarbeit},
confidential = {n},
}
- Torsten Menne:
Vergleich von CLP und ILP basierten Optimierungsstrategien am Beispiel der Codegenerierung fuer DSPs.
September 1999, M.Sc. thesis, Adviser: Steven Bashrod
[BibTeX][PDF]@mastersthesis { Menne1999,
title = {Vergleich von CLP und ILP basierten Optimierungsstrategien am Beispiel der Codegenerierung fuer DSPs},
author = {Menne, Torsten},
school = {Technische Universtit\"at Dortmund},
year = {1999},
month = {September},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/menne.ps.gz},
confidential = {n},
adviser = {Steven Bashrod},
}
- Thomas Barschdorf:
Codeerzeugung fuer den digitalen Signalprozessor TI TMS320C5x.
September 1999, M.Sc. thesis, Adviser: Rainer Leupers
[BibTeX][PDF]@mastersthesis { Barschdorf1999,
title = {Codeerzeugung fuer den digitalen Signalprozessor TI TMS320C5x},
author = {Barschdorf, Thomas},
school = {Technische Universtit\"at Dortmund},
year = {1999},
month = {September},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/barschdorf.ps.gz},
confidential = {n},
adviser = {Rainer Leupers},
}
- Björn Franke:
Analysen und Methoden optimierender Compiler zur Steigerung der Effizienz von Speicherzugriffen in eingebetteten Systemen.
August 1999, M.Sc. thesis, Adviser: Steven Bashrod
[BibTeX][PDF]@mastersthesis { Franke1999,
title = {Analysen und Methoden optimierender Compiler zur Steigerung der Effizienz von Speicherzugriffen in eingebetteten Systemen},
author = {Franke, Bj\"orn},
school = {Technische Universtit\"at Dortmund},
year = {1999},
month = {August},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/franke.pdf},
confidential = {n},
adviser = {Steven Bashrod},
}
- Stefan Rave:
Entwurf und Realisierung eines skalierbaren FPGA-Prototypenboards.
April 1999, M.Sc. thesis, Adviser: Birger Landwehr
[BibTeX][PDF]@mastersthesis { Rave1999,
title = {Entwurf und Realisierung eines skalierbaren FPGA-Prototypenboards},
author = {Rave, Stefan},
school = {Technische Universtit\"at Dortmund},
year = {1999},
month = {April},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/rave.ps.gz},
confidential = {n},
adviser = {Birger Landwehr},
}
1998
- Christian Schaefer:
Interface-Synthese fuer inkompatible Protokolle.
1998, M.Sc. thesis, Adviser: Ralf Niemann
[BibTeX][PDF]@mastersthesis { Schaefer1998,
title = {Interface-Synthese fuer inkompatible Protokolle},
author = {Schaefer, Christian},
school = {Technische Universtit\"at Dortmund},
year = {1998},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/schaefer_1998.pdf},
confidential = {n},
adviser = {Ralf Niemann},
}
- Heiko Falk:
Hardware-Partitionierung für Prototypen-Boards.
August 1998, M.Sc. thesis, Adviser: Ralf Niemann
[BibTeX][PDF]@mastersthesis { Falk1998,
title = {Hardware-Partitionierung f\"ur Prototypen-Boards},
author = {Falk, Heiko},
school = {Technische Universtit\"at Dortmund},
year = {1998},
month = {August},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/falk.pdf},
confidential = {n},
adviser = {Ralf Niemann},
}
1997
- Markus Lorenz:
Mikroarchitektur-Synthese mit genetischen Algorithmen.
November 1997, M.Sc. thesis, Adviser: Birger Landwehr
[BibTeX][PDF]@mastersthesis { Lorenz1997,
title = {Mikroarchitektur-Synthese mit genetischen Algorithmen},
author = {Lorenz, Markus},
school = {Technische Universtit\"at Dortmund},
year = {1997},
month = {November},
file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/lorenz.ps.gz},
confidential = {n},
adviser = {Birger Landwehr},
}
1974
- Peter Marwedel:
Entwicklung und Anwendung von methoden zur stochastischen Behandlung von linearen und nichtlinearen Systemen am Beispiel eines Radiofrequenzspektrometers.
1974, PhD thesis
[BibTeX]@phdthesis { marw:74:phd,
title = {Entwicklung und Anwendung von methoden zur stochastischen Behandlung von linearen und nichtlinearen Systemen am Beispiel eines Radiofrequenzspektrometers},
author = {Marwedel, Peter},
school = {Institut f\"ur Angewandte Physik der Universit\"at Kiel},
year = {1974},
confidential = {n},
}
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