| Christian Hakert.
Memory Access Analysis and Endurance Leveling Approaches for Non-volatile Working Memory Systems.
Master's Thesis, 2019
[BibTeX][PDF][Abstract]@mastersthesis { HakertMA,
title = {Memory Access Analysis and Endurance Leveling Approaches for Non-volatile Working Memory Systems},
author = {Hakert, Christian},
school = {TU Dortmund},
year = {2019},
keywords = {nvm-oma},
file = {https://ls12-joomla-host.cs.tu-dortmund.de/daes/media/documents/theses/2019-hakert.pdf},
confidential = {n},
abstract = {Emerging technologies for non-volatile memory (NVM), such as phase-change memory (PCM), ferroelectric RAM (FeRAM), spin-transfer torque magnetoresistive RAM (STT-MRAM) and many more, have been considered as a replacement for DRAM and storage due to low leakage power, high capacity and fast access times. A major disadvantage of some NVMs is the significantly lower write endurance compared to DRAM. To tackle this issue, several in-memory wear-leveling approaches have been proposed in literature, targeting the program execution to make the memory write usage more uniform. These approaches operate on different granularities, like memory pages, cache-lines, big segments, etc. Aging-aware approaches take the current wear-level of memory cells into account to make the best wear-leveling decisions, while other approaches try to balance the wear-level in a random based manner or in a circular manner. However, most approaches propose specialized hardware controllers to collect the aging information and to perform wear-leveling actions, like relocations of memory regions.
As specialized hardware may be hard to build at all, this thesis proposes so-called software only wear-leveling, which only makes use of commonly available hardware components. Aging-aware wear-leveling on the granularity of virtual memory pages is achieved by estimating the cell aging by a statistical runtime approximation. As an extension to this, fine-grained wear-leveling for the stack region of applications is achieved by relocating the stack periodically in a circular manner through a reserved memory region.
The necessity for commonly available hardware components only allows the techniques to be executed in a full system simulation setup (i.e. gem5 as a simulator for an ARM CPU and NVMain 2.0 as a simulator for the NVM) for evaluation purposes. The results show that coarse-grained aging-aware wear-leveling with approximated cell ages works out, but cannot resolve non-uniform write distributions within virtual memory pages. This limits the gained improvement of the memory lifetime up to a factor of ≈ 13 compared to the baseline without any wear-leveling. Combining the coarse-grained approach with the fine- grained stack wear-leveling technique, the non-uniformity caused by the stack region can be resolved and the evaluations result in an improvement of the memory lifetime up to a factor of ≈ 900 compared to the baseline.},
adviser = {Dr. Kuan-Hsun Chen},
}
Emerging technologies for non-volatile memory (NVM), such as phase-change memory (PCM), ferroelectric RAM (FeRAM), spin-transfer torque magnetoresistive RAM (STT-MRAM) and many more, have been considered as a replacement for DRAM and storage due to low leakage power, high capacity and fast access times. A major disadvantage of some NVMs is the significantly lower write endurance compared to DRAM. To tackle this issue, several in-memory wear-leveling approaches have been proposed in literature, targeting the program execution to make the memory write usage more uniform. These approaches operate on different granularities, like memory pages, cache-lines, big segments, etc. Aging-aware approaches take the current wear-level of memory cells into account to make the best wear-leveling decisions, while other approaches try to balance the wear-level in a random based manner or in a circular manner. However, most approaches propose specialized hardware controllers to collect the aging information and to perform wear-leveling actions, like relocations of memory regions.
As specialized hardware may be hard to build at all, this thesis proposes so-called software only wear-leveling, which only makes use of commonly available hardware components. Aging-aware wear-leveling on the granularity of virtual memory pages is achieved by estimating the cell aging by a statistical runtime approximation. As an extension to this, fine-grained wear-leveling for the stack region of applications is achieved by relocating the stack periodically in a circular manner through a reserved memory region.
The necessity for commonly available hardware components only allows the techniques to be executed in a full system simulation setup (i.e. gem5 as a simulator for an ARM CPU and NVMain 2.0 as a simulator for the NVM) for evaluation purposes. The results show that coarse-grained aging-aware wear-leveling with approximated cell ages works out, but cannot resolve non-uniform write distributions within virtual memory pages. This limits the gained improvement of the memory lifetime up to a factor of ≈ 13 compared to the baseline without any wear-leveling. Combining the coarse-grained approach with the fine- grained stack wear-leveling technique, the non-uniformity caused by the stack region can be resolved and the evaluations result in an improvement of the memory lifetime up to a factor of ≈ 900 compared to the baseline.
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| Christian Hakert, Kuan-Hsun Chen, Mikail Yayla, Georg von der Brüggen, Sebastian Bloemeke and Jian-Jia Chen.
Software-Based Memory Analysis Environments for In-Memory Wear-Leveling.
In 25th Asia and South Pacific Design Automation Conference ASP-DAC 2020, Invited Paper
2019
[BibTeX][Abstract]@inproceedings { nvmsimulator,
author = {Hakert, Christian and Chen, Kuan-Hsun and Yayla, Mikail and Br\"uggen, Georg von der and Bloemeke, Sebastian and Chen, Jian-Jia},
title = {Software-Based Memory Analysis Environments for In-Memory Wear-Leveling},
booktitle = {25th Asia and South Pacific Design Automation Conference ASP-DAC 2020, Invited Paper},
year = {2019},
keywords = {kuan, nvm-oma, georg},
confidential = {n},
abstract = {Emerging non-volatile memory (NVM) architectures are considered as a replacement for DRAM and storage in the near future, since NVMs provide low power consumption, fast access speed, and low unit cost. Due to the lower write-endurance of NVMs, several in-memory wear-leveling techniques have been studied over the last years. Since most approaches propose or rely on specialized hardware, the techniques are often evaluated based on assumptions and in-house simulations rather than on real systems. To address this issue, we develop a setup consisting of a gem5 instance and an NVMain2.0 instance, which simulates an entire system (CPU, peripherals, etc.) together with an NVM plugged into the system. Taking a recorded memory access pattern from a low-level simulation into consideration to design and optimize wear-leveling techniques as operating system services allows a cross-layer design of wear- leveling techniques. With the insights gathered by analyzing the recorded memory access patterns, we develop a software-only wear-leveling solution, which does not require special hardware at all. This algorithm is evaluated afterwards by the full system simulation.},
}
Emerging non-volatile memory (NVM) architectures are considered as a replacement for DRAM and storage in the near future, since NVMs provide low power consumption, fast access speed, and low unit cost. Due to the lower write-endurance of NVMs, several in-memory wear-leveling techniques have been studied over the last years. Since most approaches propose or rely on specialized hardware, the techniques are often evaluated based on assumptions and in-house simulations rather than on real systems. To address this issue, we develop a setup consisting of a gem5 instance and an NVMain2.0 instance, which simulates an entire system (CPU, peripherals, etc.) together with an NVM plugged into the system. Taking a recorded memory access pattern from a low-level simulation into consideration to design and optimize wear-leveling techniques as operating system services allows a cross-layer design of wear- leveling techniques. With the insights gathered by analyzing the recorded memory access patterns, we develop a software-only wear-leveling solution, which does not require special hardware at all. This algorithm is evaluated afterwards by the full system simulation.
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