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Design und Optimization of Non-Volatile One Memory Architecture: NVM-OMA

Abstract

Different forms of non-volatile memories (NVMs) have been introduced in the past decades. The recent development of NVMs has led to a promising future for building extra low-power computing systems when a NVM device is used as the media of both main memory and storage at the same time. However, most of the existing research results and system designs still consider NVM devices as additional memory or storage.

In this project, we consider the visionary embedded system architecture of using NVMs to replace DRAM, i.e., NVM is used as both main memory and storage (called one-memory architecture).

The project is coupled by two principle investigators (PI) from TU Dortmund and KIT in Germany and three PIs from Academia Sinica, National Taiwan University, and Chang Gung University in Taiwan. The applicant groups are domain experts in hardware-software codesign, embedded systems, non-volatile memories, power-efficient designs, and real-time systems.

Our project intends to provide the fundamental cornerstone of one-memory architectures that can be used to enable normally-off computing and improve battery-driven embedded systems. Our project aims to enable the effectiveness of one-memory architectures by performing design-space exploration in hardware and software designs, and by integrating analytical as well as optimized resource management in operating systems.

 

People in Germany

Prof. Dr. Jian-Jia Chen (TU Dortmund)

Prof. Dr.-Ing. Jörg Henkel (KIT)

Jun.-Prof. Dr.-Ing Hussam Amrouch (Uni Stuttgart)

Dr.-Ing. Lars Bauer (KIT)

Dr.-Ing. Kuan-Hsun Chen (TU Dortmund)

Christian Hakert, M.Sc. (TU Dortmund)

Mikail Yayla, M.Sc. (TU Dortmund)
People in Taiwan

Prof. Tei-Wei Kuo

Prof. Chia-Lin Yang

Prof. Yuan-Hao Chang

  • Chun-Feng Wu

Prof. Shou-Han Chen

Prof. Che-Wei Chang

Prof. Hsiang-Yun Cheng

 

 

Project Relevant Publications (2019-2020):

 

  • “NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN”, submitted to IEEE Nonvolatile Memory Systems and Applications Symposium (NVMSA), 2020.
  • “How to Cultivate a Green Decision Tree without Loss of Accuracy?" ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020.
  • "Replanting Your Forest: NVM-friendly Bagging Strategy for Random Forest," IEEE Nonvolatile Memory Systems and Applications Symposium (NVMSA), Hangzhou, China, Aug. 18-21, 2019. (Best Paper Award)
  • "Adaptive Memory and Storage Fusion on Non-Volatile One-Memory System,” in IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), Hangzhou, China, Aug. 18-21, 2019.
  • "The Best of Both Worlds: On Exploiting Bit-Alterable NAND Flash for Lifetime and Read Performance Optimization," ACM/IEEE Design Automation Conference (DAC), Las Vegas, Nevada, USA, Jun. 2-6, 2019.

 

 

Activity Timeline
  • 01.02.2020 -- Tutorial @ DATE 2021 (https://www.date-conference.com/tutorial/m03)
  • 27.07.2020 -- Midterm Workshop @ Zoom
  • 12.06.2020 -- Administrative Meeting @ Skype
  • 17.02.2020 -- Project meeting @ Skype
  • 03.12.2019 -- Project meeting @ KIT (Germany)
  • 25.10.2019 -- Face-to-face meeting with NEC @ Heidelberg (Germany)
  • 22.10.2019 -- Programming tutorial for NVM simulations @ TU Dortmund (Germany)
  • 01.10.2019 -- Project meeting @ Dortmund (Germany)
  • 16.05.2019 -- Project meeting @ KIT (Germany)
  • 04.03.2019 -- Kickoff workshop @ Academia Sinica (Taiwan)
  • 12.02.2019 -- Project meeting @ KIT (Germany)

 

Publications, Reports and Theses

2021
Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang and Tei-Wei Kuo.
Future Computing Platform Design: A Cross-Layer Design Approach.
In Design, Automation and Test in Europe Conference (DATE)
2021
[BibTeX][PDF][Abstract]
Mikail Yayla, Kuan-Hsun Chen, Georgios Zervakis, Jörg Henkel, Jian-Jia Chen and Hussam Amrouch.
FeFET and NCFET for Future Neural Networks: Visions and Opportunities.
In Design, Automation and Test in Europe Conference (DATE)
2021
[BibTeX][PDF][Abstract]
Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler and Mikail Yayla.
Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance.
In Design, Automation and Test in Europe Conference (DATE), accepted
2021, Best Paper Award Candidate
[BibTeX][PDF][Abstract]
2020
Ruoheng Ma.
A RISCV Emulation Board for Non-Volatile Memory.
2020
[BibTeX][PDF][Abstract]
Manuel Killinger.
Implementation of a Memory Access Trace Unit for a RISC-V SoC.
2020
[BibTeX][PDF][Abstract]
Christian Hakert, Kuan-Hsun Chen, Mikail Yayla, Georg von der Brüggen, Sebastian Bloemeke and Jian-Jia Chen.
Software-Based Memory Analysis Environments for In-Memory Wear-Leveling.
In 25th Asia and South Pacific Design Automation Conference ASP-DAC 2020, Invited Paper
Beijing, China, 2020
[BibTeX][PDF][Abstract]
Wei-Chun Cheng, Shuo-Han Chen, Yuan-Hao Chang, Kuan-Hsun Chen, Jian-Jia Chen, Tseng-Yi Chen, Ming-Chang Yang and Wei-Kuan Shih.
NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN.
In 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)
Virtual Conference, 2020
[BibTeX][PDF][Abstract]
Christian Hakert, Kuan-Hsun Chen, Simon Kuenzer, Sharan Santhanam, Shuo-Han Chen, Yuan-Hao Chang, Felipe Huici and Jian-Jia Chen.
Split’n Trace NVM: Leveraging Library OSes for Semantic Memory Tracing.
In 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)
Virtual Conference, 2020
[BibTeX][PDF][Abstract]
Dennis Morczinek.
Configurable FPGA-based Access Latency Emulation for Non-Volatile Main Memory.
Bachelor Thesis, 2020
[BibTeX][PDF][Abstract]
Junior Delrich Kamtchogom Namtchueng.
Extendable Hardware-Based Main Memory Access Snooping for Non-volatile Memory Simulations and Analysis.
Bachelor Thesis, 2020
[BibTeX][PDF][Abstract]
Christian Hakert, Kuan-Hsun Chen, Paul R. Genssler, Georg Brüggen, Lars Bauer, Hussam Amrouch, Jian-Jia Chen and Jörg Henkel.
SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory.
CoRR abs/2004.03244
2020
[BibTeX][Link][Abstract]
Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler and Mikail Yayla.
Towards Explainable Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks.
CoRR abs/2002.00909
2020
[BibTeX][Link][Abstract]
2019
Christian Hakert.
Memory Access Analysis and Endurance Leveling Approaches for Non-volatile Working Memory Systems.
Master's Thesis, 2019
[BibTeX][PDF][Abstract]
Sebastian Blömeke.
Analysis and Optimization of Trace-Based Simulator for Non-Volatile Main Memory.
Bachelor Thesis, 2019
[BibTeX][Abstract]
Christian Hakert, Mikail Yayla, Kuan-Hsun Chen, Georg von der Brüggen, Jian-Jia Chen, Sebastian Buschjäger, Katharina Morik, Paul R. Genssler, Lars Bauer, Hussam Amrouch and Jörg Henkel.
Stack Usage Analysis for Efficient Wear Leveling in Non-Volatile Main Memory Systems.
In 1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)
Alberta, Canada, 2019
[BibTeX][PDF][Abstract]

 

 

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Tei-Wei Kuo