@inproceedings { Cheng/etal/2021,
  author = {Cheng, Hsiang-Yun and Wu, Chun-Feng and Hakert, Christian and Chen, Kuan-Hsun and Chang, Yuan-Hao and Chen, Jian-Jia and Yang, Chia-Lin and Kuo, Tei-Wei},
  title = {Future Computing Platform Design: A Cross-Layer Design Approach},
  booktitle = {Design, Automation and Test in Europe Conference (DATE)},
  year = {2021},
  keywords = {kuan, nvm-oma},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2021datecross.pdf},
  confidential = {n},
  abstract = {Future computing platforms are facing a paradigm shift with the emerging resistive memory technologies. First, they offer fast memory accesses and data persistence in a single large-capacity device deployed on the memory bus, blurring the boundary between memory and storage. Second, they enable computing-in-memory for neuromorphic computing to mitigate costly data movements. Due to the non-ideality of these resistive memory devices at the moment, we envision that cross-layer design is essential to bring such a system into practice. In this paper, we showcase a few examples to demonstrate how cross-layer design can be developed to fully exploit the potential of resistive memories and accelerate its adoption for future computing platforms.},
}

@inproceedings { yayla/etal/2021,
  author = {Yayla, Mikail and Chen, Kuan-Hsun and Zervakis, Georgios and Henkel, J\"org and Chen, Jian-Jia and Amrouch, Hussam},
  title = {FeFET and NCFET for Future Neural Networks: Visions and Opportunities},
  booktitle = {Design, Automation and Test in Europe Conference (DATE)},
  year = {2021},
  keywords = {kuan, nvm-oma},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2021datefefet.pdf},
  confidential = {n},
  abstract = {The goal of this special session paper is to introduce and discuss different emerging technologies for logic circuitry and memory as well as new lightweight architectures for neural networks. We demonstrate how the ever-increasing complexity in Artificial Intelligent (AI) applications, resulting in an immense increase in the computational power, necessitates inevitably employing innovations starting from the underlying devices all the way up to the architectures. Two different promising emerging technologies will be presented: (i) Negative Capacitance Field-Effect Transistor (NCFET) as a new beyond-CMOS technology with advantages for offering low power and/or higher accuracy for neural network inference. (ii) Ferroelectric FET (FeFET) as a novel non-volatile, area-efficient and ultra-low power memory device. In addition, we demonstrate how Binary Neural Networks (BNNs) offer a promising alternative for traditional Deep Neural Networks (DNNs) due to its lightweight hardware implementation. Finally, we present the challenges from combining FeFET-based NVM with NNs and summarize our perspectives for future NNs and the vital role that emerging technologies may play.},
}

@inproceedings { buschjaeger/etal/2021,
  author = {Buschj\"ager, Sebastian and Chen, Jian-Jia and Chen, Kuan-Hsun and G\"unzel, Mario and Hakert, Christian and Morik, Katharina and Novkin, Rodion and Pfahler, Lukas and Yayla, Mikail},
  title = {Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance},
  booktitle = {Design, Automation and Test in Europe Conference (DATE), accepted},
  year = {2021},
  note = {Best Paper Award Candidate},
  keywords = {kuan, nvm-oma},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2021dateyayla.pdf},
  confidential = {n},
  abstract = {To overcome the memory wall in neural network (NN) inference systems, recent studies have proposed to use approximate memory, in which the supply voltage and access latency parameters are tuned, for lower energy consumption and faster access at the cost of reliability. To tolerate the occuring bit errors, the state-of-the-art approaches apply bit flip injections to the NNs during training, which require high overheads and do not scale well for large NNs and high bit error rates. In this work, we focus on binarized NNs (BNNs), whose simpler structure allows better exploration of bit error tolerance metrics based on margins. We provide formal proofs to quantify the maximum number of bit flips that can be tolerated. With the proposed margin-based metrics and the well-known hinge loss for maximum margin classification in support vector machines (SVMs), we are able to construct a modified hinge loss (MHL) to train BNNs for bit error tolerance without any bit flip injections. Our experimental results indicate that the MHL enables the possibility for BNNs to tolerate higher bit error rates than with bit flip training and, therefore, allows to further lower the requirements on approximate memories used for BNNs. },
}

@misc { RMaMA,
  author = {Ma, Ruoheng},
  title = {A RISCV Emulation Board for Non-Volatile Memory},
  howpublished = {KIT},
  year = {2020},
  keywords = {nvm-oma, kit},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/riscv.pdf},
  confidential = {n},
  abstract = {As DRAM is facing some problems such as limited scalability and huge power
consumption, researchers are turning their focus on the emerging Non-Volatile Memory
(NVM) technologies, like Phase-Change RAM (PRAM), Spin-Transfer Torque RAM (STT-RAM)
and Resistive RAM (ReRAM), to get rid of these problems. Compared to DRAM, NVM is non
volatile and has higher density. Moreover, in contrast to flash memory, NVM are byte
addressable. Therefore, they can be considered as a candidate for replacing traditional
DRAM. In order to explore the characteristics of different NVM technologies, in this thesis,
an emulation board with parameterizable memory access latency is built upon a platform
called FU500, which utilizing the open-source instruction set architecture RISCV, to ensure
flexibility and extensibility for further research. Moreover, a benchmark suite comprising
MiBench and Tinymembench is also built for benchmarking this board.},
}

@misc { BAmkTrace,
  author = {Killinger, Manuel},
  title = {Implementation of a Memory Access Trace Unit for a RISC-V SoC},
  year = {2020},
  keywords = {soc, tracing, fpga, risc-v, memory, wear-leveling, kit, nvm-oma},
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/killinger.pdf},
  confidential = {n},
  abstract = {{One of the most important aspects of testing and analyzing embedded systems is the system monitoring itself. Newly developed System on a Chip can be verified and tested using simulation software, with the drawback of often being computationally expensive or slow. Especially of interest is the read and write behavior of SoCs. This work presents the implementation of a Trace Unit, developed for the Freedom U500 SoC. It is a non-invasive component that can monitor all memory accesses flowing to and from the main memory. The Trace Unit is integrated into U500\^a€TMs memory subsystem to expose the access behavior during the execution of various benchmarks, and the results are collected and presented.}
}
@techreport{scheidtSA,
    author = {David Scheidt},
    title = {Dynamic Memory Placement of Applications on Extreme Resource Constrained Hardware},
    institution = {TU Dortmund},
    year = {2020},
    keywords = {nvm-oma,thesis},
    file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/2020-scheidt.pdf},
    confidential = {n}
},
}

@inproceedings { nvmsimulator,
  author = {Hakert, Christian and Chen, Kuan-Hsun and Yayla, Mikail and Br\"uggen, Georg von der and Bloemeke, Sebastian and Chen, Jian-Jia},
  title = {Software-Based Memory Analysis Environments for In-Memory Wear-Leveling},
  booktitle = {25th Asia and South Pacific Design Automation Conference ASP-DAC 2020, Invited Paper},
  year = {2020},
  address = {Beijing, China},
  keywords = {kuan, nvm-oma, georg},
  file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2020-aspdac-nvm.pdf},
  confidential = {n},
  abstract = {Emerging non-volatile memory (NVM) architectures are considered as a replacement for DRAM and storage in the near future, since NVMs provide low power consumption, fast access speed, and low unit cost. Due to the lower write-endurance of NVMs, several in-memory wear-leveling techniques have been studied over the last years. Since most approaches propose or rely on specialized hardware, the techniques are often evaluated based on assumptions and in-house simulations rather than on real systems. To address this issue, we develop a setup consisting of a gem5 instance and an NVMain2.0 instance, which simulates an entire system (CPU, peripherals, etc.) together with an NVM plugged into the system. Taking a recorded memory access pattern from a low-level simulation into consideration to design and optimize wear-leveling techniques as operating system services allows a cross-layer design of wear- leveling techniques. With the insights gathered by analyzing the recorded memory access patterns, we develop a software-only wear-leveling solution, which does not require special hardware at all. This algorithm is evaluated afterwards by the full system simulation.},
}

@inproceedings { most2020nvmsa,
  author = {Cheng, Wei-Chun and Chen, Shuo-Han and Chang, Yuan-Hao and Chen, Kuan-Hsun and Chen, Jian-Jia and Chen, Tseng-Yi and Yang, Ming-Chang and Shih, Wei-Kuan},
  title = {NS-FTL: Alleviating the Uneven Bit-Level Wearing of NVRAM-based FTL via NAND-SPIN},
  booktitle = {9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)},
  year = {2020},
  address = {Virtual Conference},
  keywords = {kuan, nvm-oma, },
  file = {http://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2020nvmsa-ftl.pdf},
  confidential = {n},
  abstract = {Non-Volatile random access memory (NVRAM) has been regarded as a promising DRAM alternative with its non volatility, near-zero idle power consumption, and byte addressability. In particular, some NVRAM devices, such as Spin Torque Transfer (STT) RAM, can provide the same or better access performance and lower power consumption when compared with dynamic random access memory (DRAM). These nice features make NVRAM become an attractive DRAM replacement on NAND flash storage for resolving the management overhead of the flash translation layer (FTL). For instance, when adopting NVRAM for storing the mapping entries of FTL, the overheads of loading and storing the mapping entries between the non-volatile NAND flash and the volatile DRAM can be eliminated. Nevertheless, due to the limited lifetime constraint of NVRAM, the bit-level update behavior of FTL may lead to the issue of uneven bit-level wearing and the lifetime capacity of those less-worn NVRAM cells could be underutilized. Such an observation motivates this study to utilize the emerging NAND-like Spin Torque Transfer memory (NAND-SPIN) for alleviating the uneven bit-level wearing of NVRAM-based FTL and making the best of the lifetime capacity of each NAND-SPIN cell. The experimental results show that the proposed design can effectively avoid the uneven bit-level wearing, when compared with page-based FTL on NAND-SPIN.},
}

@inproceedings { hakert2020nvmsa,
  author = {Hakert, Christian and Chen, Kuan-Hsun and Kuenzer, Simon and Santhanam, Sharan and Chen, Shuo-Han and Chang, Yuan-Hao and Huici, Felipe and Chen, Jian-Jia},
  title = {Split’n Trace NVM: Leveraging Library OSes for Semantic Memory Tracing},
  booktitle = {9th Non-Volatile Memory Systems and Applications Symposium (NVMSA)},
  year = {2020},
  address = {Virtual Conference},
  keywords = {kuan, nvm-oma, },
  file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/2020-nvmsa-hakert.pdf},
  confidential = {n},
  abstract = {With the rise of non-volatile memory (NVM) as a replacement for traditional main memories (e.g. DRAM), memory access analysis is becoming an increasingly important topic. NVMs suffer from technical shortcomings as such as reduced cell endurance which call for precise memory access analysis in order to design maintenance strategies that can extend the memory’s lifetime. While existing memory access analyzers trace memory accesses at various levels, from the application level with code instrumentation, down to the hardware level where software is executed on special analysis hardware, they usually interpret main memory as a consecutive area, without investigating the application semantics of different memory regions.
In contrast, this paper presents a memory access simulator, which splits the main memory into semantic regions and enriches the simulation result with semantics from the analyzed application. We leverage a library-based operating system called Unikraft by ascribing memory regions of the simulation to the relevant OS libraries. This novel approach allows us to derive a detailed analysis of which libraries (and thus functionalities) are responsible for which memory access patterns. Through offline profiling with our simulator, we provide a fine-granularity analysis of memory access patterns that provide insights for the design of efficient NVM maintenance strategies.},
}

@bachelorthesis { morczinek2020ba,
  title = {Configurable FPGA-based Access Latency Emulation for Non-Volatile Main Memory},
  author = {Morczinek, Dennis},
  school = {TU Dortmund},
  year = {2020},
  keywords = {nvm-oma},
  file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/2020-morczinek.pdf},
  confidential = {n},
  abstract = {Since the drawbacks of using non-volatile memory (NVM) technologies as main memory
are being addressed by researchers, its use as an energy efficient alternative to traditional
DRAM is more interesting than ever. The impact of the greater memory access latencies
of NVM compared to DRAM on a system can be investigated in systems that utilize at
least one type of NVM as main memory. In many cases those systems do not exist yet,
so the research has to be conducted on non-volatile main memory (NVMM) emulators or
simulators. Yu Omori et al. developed such an emulator on an SoC-FPGA. Their emulator
injects additional read and write delays to memory accesses that are configurable by the
user. However, the configurations are applied to the whole memory of the emulator, so
emulating hybrid systems with more than one NVMM type is not possible.
This thesis extends the FPGA emulator design of Yu Omori et al. to allow the emulation
of more than one NVMM type by making it possible to define areas in the main memory
with different access latencies. The underlying emulator architecture is adapted so that
the corresponding latency for each area can be stored and the delay injection logic receives
the appropriate value when a memory access is performed. The count of definable areas
and the utilization of the FPGA are kept in balance to allow for future modifications of
the emulator design.
},
  adviser = {Christian Hakert},
}

@bachelorthesis { kamtchogom2020ba,
  title = {Extendable Hardware-Based Main Memory Access Snooping for Non-volatile Memory Simulations and Analysis},
  author = {Namtchueng, Junior Delrich Kamtchogom},
  school = {TU Dortmund},
  year = {2020},
  keywords = {nvm-oma},
  file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/kamtchogom-ba.pdf},
  confidential = {n},
  abstract = {In order to determine the internal functioning of a computer memory, a simulation is
necessary. Simulate a memory means, make read/write requests to this memory and
observe the path that the requests are going through. Knowledges about the internal
functioning is for example important to be able to give some guarantees about its latency
or its reponse time. Make this simulation implicitly means the need of a simulator.
This thesis is about designing the simulator by using an extension hardware interface of
the processor and then analysing the output values of the simulator.
The methodology followed here is, first the presentation of the hardware interface, then
the presentation of the dataflow during the different requests, then the presentation of the
design used for the simulation and finally the analysis of the simulation result.
The analysis of the simulation result showed that both part of the memory (registers and
BRAM) simulated here work perfectly. In addition, during the access to the BRAM, it
results a delay between the moment when it receives the request and the moment when
it returns a response. Beyond that, the registers and the BRAM have in common that
they have a small addressable space. To have an access to a larger space another means
(DRAM access) is slightly described.
},
  adviser = {Christian Hakert},
}

@article { hakert2020softwear,
  author = {Hakert, Christian and Chen, Kuan-Hsun and Genssler, Paul R. and Br\"uggen, Georg and Bauer, Lars and Amrouch, Hussam and Chen, Jian-Jia and Henkel, J\"org},
  title = {SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory},
  journal = {CoRR},
  year = {2020},
  volume = {abs/2004.03244},
  url = {https://arxiv.org/pdf/2004.03244.pdf},
  keywords = {kuan, nvm-oma, georg},
  confidential = {n},
  abstract = {Several emerging technologies for byte-addressable non-volatile memory (NVM) have been considered to replace DRAM as the main memory in computer systems during the last years. The disadvantage of a lower write endurance, compared to DRAM, of NVM technologies like Phase-Change Memory (PCM) or Ferroelectric RAM (FeRAM) has been addressed in the literature. As a solution, in-memory wear-leveling techniques have been proposed, which aim to balance the wear-level over all memory cells to achieve an increased memory lifetime. Generally, to apply such advanced aging-aware wear-leveling techniques proposed in the literature, additional special hardware is introduced into the memory system to provide the necessary information about the cell age and thus enable aging-aware wear-leveling decisions.
This paper proposes software-only aging-aware wear-leveling based on common CPU features and does not rely on any additional hardware support from the memory subsystem. Specifically, we exploit the memory management unit (MMU), performance counters, and interrupts to approximate the memory write counts as an aging indicator. Although the software-only approach may lead to slightly worse wear-leveling, it is applicable on commonly available hardware. We achieve page-level coarse-grained wear-leveling by approximating the current cell age through statistical sampling and performing physical memory remapping through the MMU. This method results in non-uniform memory usage patterns within a memory page. Hence, we further propose a fine-grained wear-leveling in the stack region of C / C++ compiled software.
By applying both wear-leveling techniques, we achieve up to 78.43% of the ideal memory lifetime, which is a lifetime improvement of more than a factor of 900 compared to the lifetime without any wear-leveling. },
}

@article { buschjger2020explainable,
  author = {Buschj\"ager, Sebastian and Chen, Jian-Jia and Chen, Kuan-Hsun and G\"unzel, Mario and Hakert, Christian and Morik, Katharina and Novkin, Rodion and Pfahler, Lukas and Yayla, Mikail},
  title = {Towards Explainable Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks},
  journal = {CoRR},
  year = {2020},
  volume = {abs/2002.00909},
  url = {https://arxiv.org/pdf/2002.00909.pdf},
  keywords = {kuan, nvm-oma, mario},
  confidential = {n},
  abstract = {Non-volatile memory, such as resistive RAM (RRAM), is an emerging energy-efficient storage, especially for low-power machine learning models on the edge. It is reported, however, that the bit error rate of RRAMs can be up to 3.3% in the ultra low-power setting, which might be crucial for many use cases. Binary neural networks (BNNs), a resource efficient variant of neural networks (NNs), can tolerate a certain percentage of errors without a loss in accuracy and demand lower resources in computation and storage. The bit error tolerance (BET) in BNNs can be achieved by flipping the weight signs during training, as proposed by Hirtzlin et al., but their method has a significant drawback, especially for fully connected neural networks (FCNN): The FCNNs overfit to the error rate used in training, which leads to low accuracy under lower error rates. In addition, the underlying principles of BET are not investigated. In this work, we improve the training for BET of BNNs and aim to explain this property. We propose straight-through gradient approximation to improve the weight-sign-flip training, by which BNNs adapt less to the bit error rates. To explain the achieved robustness, we define a metric that aims to measure BET without fault injection. We evaluate the metric and find that it correlates with accuracy over error rate for all FCNNs tested. Finally, we explore the influence of a novel regularizer that optimizes with respect to this metric, with the aim of providing a configurable trade-off in accuracy and BET.},
}

@mastersthesis { HakertMA,
  title = {Memory Access Analysis and Endurance Leveling Approaches for Non-volatile Working Memory Systems},
  author = {Hakert, Christian},
  school = {TU Dortmund},
  year = {2019},
  keywords = {nvm-oma},
  file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/theses/2019-hakert.pdf},
  confidential = {n},
  abstract = {Emerging technologies for non-volatile memory (NVM), such as phase-change memory (PCM), ferroelectric RAM (FeRAM), spin-transfer torque magnetoresistive RAM (STT-MRAM) and many more, have been considered as a replacement for DRAM and storage due to low leakage power, high capacity and fast access times. A major disadvantage of some NVMs is the significantly lower write endurance compared to DRAM. To tackle this issue, several in-memory wear-leveling approaches have been proposed in literature, targeting the program execution to make the memory write usage more uniform. These approaches operate on different granularities, like memory pages, cache-lines, big segments, etc. Aging-aware approaches take the current wear-level of memory cells into account to make the best wear-leveling decisions, while other approaches try to balance the wear-level in a random based manner or in a circular manner. However, most approaches propose specialized hardware controllers to collect the aging information and to perform wear-leveling actions, like relocations of memory regions.
As specialized hardware may be hard to build at all, this thesis proposes so-called software only wear-leveling, which only makes use of commonly available hardware components. Aging-aware wear-leveling on the granularity of virtual memory pages is achieved by estimating the cell aging by a statistical runtime approximation. As an extension to this, fine-grained wear-leveling for the stack region of applications is achieved by relocating the stack periodically in a circular manner through a reserved memory region.
The necessity for commonly available hardware components only allows the techniques to be executed in a full system simulation setup (i.e. gem5 as a simulator for an ARM CPU and NVMain 2.0 as a simulator for the NVM) for evaluation purposes. The results show that coarse-grained aging-aware wear-leveling with approximated cell ages works out, but cannot resolve non-uniform write distributions within virtual memory pages. This limits the gained improvement of the memory lifetime up to a factor of ≈ 13 compared to the baseline without any wear-leveling. Combining the coarse-grained approach with the fine- grained stack wear-leveling technique, the non-uniformity caused by the stack region can be resolved and the evaluations result in an improvement of the memory lifetime up to a factor of ≈ 900 compared to the baseline.},
  adviser = {Prof. Dr. Jian-Jia Chen and Dr. Kuan-Hsun Chen},
}

@bachelorthesis { bloemeke2019,
  title = {Analysis and Optimization of Trace-Based Simulator for Non-Volatile Main Memory},
  author = {Bl\"omeke, Sebastian},
  school = {TU Dortmund},
  year = {2019},
  keywords = {nvm-oma, thesis},
  confidential = {n},
  abstract = {In the last years, new Technologies for non-volatile memory (NVM) emerged as a replacement for storage and RAM, due to their fast access times, low leakage power and high capacity. Two recent examples would be spin transfer torque magnetoresistive RAM (STT-MRAM) [3] and phase change memory (PCM) like 3D-XPoint in Intels Optane Series. The major drawback of NVM especially as a replacement for RAM is the low write endurance. There are hardware and software solutions for this problem [4], however to test and validate them modified hardware or specialized simulation software is needed. 
In academic research it is a popular choice to simulate a full hardware setup with the software gem5 or the behavior of NVM with the software NVMain, but even short simulations in NVMain will generate trace files of tens of gigabyte. The volume of the trace files is slowing down both the simulation speed and the post-processing of the results. In this thesis i will describe and implement some optimizations to NVMain’s trace file writer which will result in a 30% reduction of trace file volume without data loss and the option of filtering out unnecessary data fields.},
  adviser = {Dr.-Ing Kuan-Hsun Chen, Prof. Dr. Jian-Jia Chen},
}

@inproceedings { mlcad2019stackanalysis,
  author = {Hakert, Christian and Yayla, Mikail and Chen, Kuan-Hsun and Br\"uggen, Georg von der and Chen, Jian-Jia and Buschj\"ager, Sebastian and Morik, Katharina and Genssler, Paul R. and Bauer, Lars and Amrouch, Hussam and Henkel, J\"org},
  title = {Stack Usage Analysis for Efficient Wear Leveling in Non-Volatile Main Memory Systems},
  booktitle = {1st ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)},
  year = {2019},
  address = {Alberta, Canada},
  keywords = {kuan, nvm-oma, georg},
  file = {https://ls12-www.cs.tu-dortmund.de/daes/media/documents/publications/downloads/mlcad_2019.pdf},
  confidential = {n},
  abstract = {Emerging non-volatile memory (NVM) technologies, such as Phase Change Memory (PCM), have been considered as a replacement for DRAM and storage due to their low power consumption, fast access speed, and low unit cost. Even so, some NVMs have a significantly lower write endurance and hence in-memory wear leveling is an important requirement for practical applicability. Since writes to the stack often target a small and dense memory region, generic, coarse-grained wear-leveling mechanisms (e.g. virtual memory page remapping) are not sufficient. An alternative solution is to relocate the stack memory regularly, which involves copying of the stack content. As the stack content changes in size during the execution of an application, the copy overhead can be significantly mitigated by performing the relocation when the stack size is small. In this paper, we investigate two approaches to determine points in time when the stack is small. First, we analyze the possibility to fit simple machine-learning models to the stack usage function. Precise predictions of this function enable the identification of the minimum stack size during execution. In our evaluation, the tested models provide accurate estimates of the future stack usage function for a subset of common applications. As a second approach, we analyze applications a priori and determine potential optimal points to perform relocation in the instruction stream. In detail, we deploy the application in an analysis environment, which determines a rating for each executed instruction. Based on this rating, we apply a genetic algorithm to identify the best points in the instruction stream to perform the stack relocation. This approach allows to save up to 85% of the write overhead for wear-leveling in our experiments.},
}