COOL - A Hardware/Software Co-Design Tool

COOL is a hardware/software codesign tool which has been developed for dataflow dominated systems. An overview of COOL is given in figure above. COOL uses a homogeneous system modelling approach using a subset of VHDL for specification. A graphical user interface has been developed to specify these systems in a structural and hierarchical way. These systems are stored in a system library. In addition, the graphical user interface is used to define target architectures and design constraints. The target architectures are organized in a target architecture library too. The main objective of COOL is heterogeneous implementation. Several algorithms for hardware/software partitioning have been developed allowing the designer

• to compute optimal solutions (by using an integer programming approach)
• to compute high-quality solutions in acceptable computation time (by using a combination of integer programming and a heuristic)
• to perform design space exploration (by using a genetic algorithm approach)

In contrast to all other approaches using estimation algorithms during hardware/software partitioning, COOL uses the synthesis and compilation tools to compute the value for the cost metrics. The software parts are compiled using the compilers for the target processor and the ASICs are synthesized by using high-level synthesis. As a consequence, COOL works on high-precision estimates which are stored in cost libraries. The usage of a cost library supports reuse and therefore computation time is saved. All partitioning algorithms integrated in COOL compute a mapping of the components of the system to processors and ASICs and allocate communication channels for required interfaces between hardware and software parts. In addition, a schedule is calculated defining the execution order of the system components on their resources. The co-synthesis algorithm of COOL refines the initial specification by

• implementing the abstract communication channels by adding dedicated lines to the hardware components and additional software for processors to implement communication based on memory mapped I/O,
• adding a system controller implementing a run-time scheduler steering the complete system according to the computed schedule,
• adding an I/O controller to handle input and output values,
• adding a bus arbiter to prevent bus-conflicts,
• generating a complete netlist for wiring all components.

The result of COOL is a VHDL netlist which can directly be synthesized by the high-level synthesis tool Oscar and the logic synthesis tool from Synopsys. In addition, assembler code is generated for the processors which has to be down-loaded. To validate the correct functionality of the system specification and its implementation after cosynthesis, the commercial VHDL simulator Vantage Optium has been integrated in COOL.