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Co-Synthesis in COOL

The goal of the co-synthesis approach realized in COOL is to refine the system specification by generating hardware specifications for synthesis and simulation in VHDL and software specifications for compilation in C. In the following figure, the design flow of the co-synthesis phase in COOL is depicted.

In a first step, a state-transition graph is generated representing the fundamental data structure during co-synthesis. This graph is computed using the colored partitioning graph. Then, the original system specification is refined into a set of specifications for the hardware and software parts. In this step, communication mechanisms for communication based on shared memory and message passing are inserted to replace the abstract communication channels. The refined hardware specifications represent the computational-intensive parts of the ASICs, e.g. an FIR-filter defined in the system specification. Thus, a refined hardware specification will be called data path in the following. To implement a complete hardware/software system, additional components are generated: a system controller steering the complete system, data path controllers to support hardware sharing of the data paths, an I/O controller to communicate with the environment and a bus arbiter for each bus to prevent bus conflicts. The interfaces of processors are often very different. To describe a general control mechanism for hardware/software systems using a processor as the master of the system becomes difficult. Hardware allows the implementation of concurrent processes and therefore in COOL the additional pieces will be implemented in hardware. COOL not only generates the descriptions of the hardware components and the software running on the processors, but also a netlist wiring all these hardware components and processors. This netlist represents a complete description of the hardware/software implementation which can be co-simulated or implemented by hardware synthesis and software compilation. Simulatable VHDL descriptions are often not synthesizable and vice versa. Therefore, COOL generates different hardware specifications for each component. The simulation model is executed by the commercial VHDL simulator Vantage Optium. Hardware synthesis is performed by the high-level synthesis tool Oscar and by the commercial logic synthesis tool Synopsys. There are two reasons to integrate two different synthesis tools:

  • Oscar has two restrictions, leading to unsolvable problems when connecting designs synthesized with Oscar to busses. First, Oscar does not support bi-directional signals. Second, the Z-value, being an element of data type std_logic in VHDL, is necessary for specifying the behavior of busses. However, Oscar only supports 0/1-values.
  • Oscar is a high-level synthesis tool, very well suited for data-dominated VHDL specifications. It optimizes the costs for large basic blocks, but for control-dominated specifications it results in too expensive designs, because the average size of the basic blocks is very small. For these control-dominated VHDL specifications Synopsys is used resulting in a drastic cost reduction compared to Oscar.

For this reason, Oscar and its backend tool OsBack are used for synthesizing the refined data paths in COOL. Finally, the results of OsBack and all additional hardware parts instantiated in the generated netlist are synthesized by Synopsys. With this separation, Cool was able to implement a Fuzzy-controller (specified with COOL) on a prototyping board containing a Motorola DSP56001 and two Xilinx FPGAs 4005. Without using Synopsys in addition to Oscar, this would have been impossible, because the available hardware area of these FPGAs is very small.

Hardware/Software Systems generated by COOL

The functioning of hardware/software systems generated by COOL will be described with the help of an equalizer example depicted in the following figure. To simplify the picture, some of the wires connecting components have been collapsed. These are represented by double lines.

The dotted components are additional components generated during the controller and netlist synthesis step. For the following components synthesizable and simulatable VHDL descriptions are generated:

  • system controller,
  • I/O controller,
  • bus arbiter,
  • hardware data paths,
  • hardware data path controllers and
  • bus drivers.

Processors and memories are fixed elements of the target architecture in COOL. Therefore, only pre-defined simulatable VHDL descriptions for

  • processors,
  • memories, and
  • local memories.

are used.